peb20532 Infineon Technologies Corporation, peb20532 Datasheet - Page 174

• Manufacturer Part Number: peb20532
• Description: 2 Channel Serial Optimized Communication Controller
• Manufacturer: Infineon Technologies Corporation

Data Sheet
RFTH(1:0)
Receive FIFO Threshold
This bit field defines the level up to which the SCC receive FIFO is filled
with valid data before an ’RPF’ interrupt is generated.
(In case of a ’frame end / block end’ condition the SEROCCO-M notifies
the CPU immediately, disregarding this threshold.)
The meaning depends on the selected protocol engine:
HDLC Modes:
RFTH(1:0)
’00’
’01’
’10’
’11’
ASYNC/BISYNC Mode:
RFTH(1:0)
’00’
’01’
’10’
’11’
Threshold level in number of data bytes.
32 byte
16 byte
4 byte
2 byte
Threshold level in number of data bytes (DB) and status
bytes (SB) depending on bit ’RFDF’:
RFDF = ’0’
1 DB
4 DB
16 DB
32 DB
5-174
Register Description (CCR3H)
RFDF = ’1’
1 DB + 1 SB
2 DB + 2 SB
8 DB + 8 SB
16 DB + 16 SB
PEB 20532
PEF 20532
(all modes)
2000-09-14