ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 99

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Baud Rate
Generator
with the same clock signal. The byte transmitted is replaced by the byte received,
eliminating the requirement for separate transmit-empty and receive-full status
bits. A single status bit, SPIF, is used to signify that the I/O operation is completed,
see
The SPI is double-buffered on read, but not on write. If a write is performed during
data transfer, the transfer occurs uninterrupted, and the write is unsuccessful. This
condition causes the WRITE COLLISION (WCOL) status bit in the SPIx_SR regis-
ter to be set. After a data byte is shifted, the SPI flag bit (SPIF) of the SPIx_SR
register is set.
In SPI MASTER mode, the SCK pin is an output. It idles High or Low, depending
on the CPOL bit in the SPIx_CTL register, until data is written to the shift register.
When data is written to the shift register, eight clocks are generated to shift the
eight bits of data in both directions. The SCK signal then enters the IDLE state.
Divide by Two
SPI Status Register
SPIx_SR Register
SPI Control
msb
Internal Address Databus
8-Bit Shift Register
Read Data Buffer
Figure 15. SPI Block Diagram
(SPI0_SR =
PRELIMINARY
Clock Logic
SPIx_CTL Register
lsb
B7h
, SPI1_SR =
eZ80190 Product Specification
Master
Master
Master
Slave
Slave
Slave
Control
Logic
BBh
Pin
) on page 88.
Serial Peripheral Interface
Signal
Signal
Signal
MOSI
Signal
MISO
SCK
SS
85