ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 86

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:4]
3
MIIE
2
LSIE
1
TIE
0
RIE
UART Interrupt Enable Register
The UARTx_IER register, indicated in
UART interrupts. The UARTx_IER registers share the same I/O addresses as the
BRGx_DLR_H registers.
Value
0000
0
1
0
1
0
1
0
1
Table 28. UART Interrupt Enable Registers
(UART0_IER = C1h, UART1_IER = D1h)
R/W
Description
Reserved
The modem interrupt on edge detect of status inputs is
disabled.
The modem interrupt on edge detect of status inputs is
enabled.
The line status interrupt is disabled.
The line status interrupt is enabled for receive data errors:
incorrect parity bit received, framing error, overrun error, or
break detection.
The transmit interrupt is disabled.
The transmit interrupt is enabled. An interrupt is generated
when the transmit FIFO buffer is empty indicating no bytes
are available for transmission.
The receive interrupt is disabled.
The receive interrupt and receiver time-out interrupt are
enabled. An interrupt is generated if the FIFO buffer contains
data ready for a READ or if the receiver times out.
7
0
R/W
6
0
PRELIMINARY
R/W
5
0
Table
R/W
4
0
Universal Asynchronous Receiver/Transmitter
28, is used to enable and disable
R/W
3
0
eZ80190 Product Specification
R/W
2
0
R/W
1
0
R/W
0
0
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