ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 105

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

eZ80190 Product Specification
91
Data Validity
The data on the SDA line must be stable during the High period of the clock. The
High or Low state of the data line can only change when the clock signal on the
SCL line is Low, as illustrated in
Figure
16.
SDA Signal
SCL Signal
Data Line
Change of
Stable
Data Allowed
Data Valid
2
Figure 16. I
C Clock and Data Relationship
START and STOP Conditions
2
Within the I
C bus protocol, unique situations arise which are defined as START
and STOP conditions. See
Figure
17. A High-to-Low transition on the SDA line
while SCL is High indicates a START condition. A Low-to-High transition on the
SDA line while SCL is High defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is con-
sidered to be busy after the START condition. The bus is considered to be free at
a defined time after the STOP condition.
SDA Signal
SCL Signal
P
S
Stop Condition
Start Condition
2
Figure 17. START and STOP Conditions In I
C Protocol
Transferring Data
Byte Format
Every character transferred on the SDA line must be a single 8-bit byte. The num-
ber of bytes that can be transmitted per transfer is unrestricted. Each byte must be
2
followed by an I
C Acknowledge (ACK). Data is transferred with the most signifi-
2
PS006613-0306
PRELIMINARY
I
C Serial I/O Interface