ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 153

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

Direct Memory Access Controller
PS006613-0306
DMA Programming
Note:
The eZ80190 device features two Direct Memory Access (DMA) channels. The
DMA controller can be used for direct memory to memory data transfers without
CPU intervention. There are two DMA channels, Channel 0 and Channel 1, each
featuring independent control registers. Transfers can be either in BURST mode
or CYCLE-STEAL mode.
In BURST mode, after the DMA controller gains access to the bus, it maintains
control of the bus until the block data transfer is complete for that channel. In
CYCLE-STEAL mode, after the DMA gains access to the bus, it transfers only one
byte and then returns control of the bus to the CPU for eight clock cycles. The
DMA then again requests the bus and gains access to transfer the next byte. This
process continues until the programmed number of bytes are transferred.
There are 18 registers that control DMA operation—nine control registers for DMA
channel 0 operation and nine control registers for DMA channel 1 operation. In
each channel, there are three registers for the 24-bit data transfer source address,
three registers for the 24-bit data transfer destination address, two registers for
the 16-bit byte count, and one register for DMA channel control.
If the DMA channel is enabled, it can take control of the system buses—
ADDR[23:0], DATA[7:0], RD, and WR—and direct the transfer of data between
memory locations. If the DMA channel is disabled, the DMA cannot initiate bus
requests nor transfer data. The DMA is always disabled after RESET. External
DMA master devices can force the eZ80190 device to release the bus for their
use by driving the BUSREQ pin Low. To the eZ80190 CPU, this bus request signal
operates the same as if it had originated from the internal DMA controllers. If both
of these signals should occur simultaneously, the internal DMA bus request will
hold a higher priority than a request from an external bus master device.
To configure the DMA registers for memory transfer, the Source and Destination
address registers must be programmed. The byte count registers must be pro-
grammed with the number of bytes to be transferred. The DMA Control register
must be programmed to select whether the Source and Destination address regis-
ters are incremented, decremented, or remain fixed during a transfer, whether the
DMA outputs an interrupt when finished, and what data transfer mode the DMA
employs. Finally, the DMA channel must be enabled to allow transfers to begin.
The DMA channel cannot be used to transfer data to or from internal I/O
registers. However, it can be used with external memory-mapped I/O
devices.
PRELIMINARY
eZ80190 Product Specification
Direct Memory Access Controller
139