ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 119

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
When the Bus Enable bit (ENAB) is set to 0, the I
ignored and the I
ENAB is set to 1, the I
call address if the GCE bit (I2Cx_SAR[0]) is set to 1.
When the Master Mode Start bit (STA) is set to 1, the I
and sends a START condition on the bus when the bus is free. If the STA bit is set
to 1 when the I
transmitted, then a repeated START condition is sent. If the STA bit is set to 1
when the I
transfer in SLAVE mode and then enters MASTER mode when the bus is
released. The STA bit is automatically cleared after a START condition is set. Writ-
ing a 0 to this bit produces no effect.
If the Master Mode Stop bit (STP) is set to 1 in MASTER mode, a STOP condition
is transmitted on the I
module behaves as if a STOP condition is received, but no STOP condition is
transmitted. If both STA and STP bits are set, the I
STOP condition (if in MASTER mode) and then transmits the START condition.
The STP bit is cleared automatically. Writing a 0 to this bit produces no effect.
The I
of 30 of the possible 31 I
state
ated. When IFLG is set by the I
stretched and the data transfer is suspended. When a 0 is written to IFLG, the
interrupt is cleared and the I
When the I
ing the Acknowledge clock pulse on the I
•
•
•
When ACK is cleared to 0, a NACK is sent when a data byte is received in MAS-
TER or SLAVE mode. If ACK is cleared to 0 in SLAVE TRANSMIT mode, the byte
in the I2Cx_DR register is presumed to be the last byte. After this byte is transmit-
ted, the I
does not respond to its slave address unless ACK is set.
Either the whole of a 7-bit slave address or the first or second byte of a 10-bit
slave address is received
The general call address is received and the General Call Enable bit in
I2Cx_SAR is set to 1
A data byte is received in MASTER or SLAVE mode
2
F8h
C Interrupt Flag (IFLG) is set to 1 automatically when the device enters any
2
. If IFLG is set to 1 and the IEN bit is also set to 1, an interrupt is gener-
C block enters state
2
2
C block is being accessed in SLAVE mode, the I
C Acknowledge bit (ACK) is set to 1, an acknowledgement is sent dur-
2
C module is already in MASTER mode and one or more bytes are
2
C module does not respond to any address on the bus. When
2
2
C bus. If the STP bit is set to 1 in SLAVE mode, the I
C responds to calls to its slave address and to the general
2
C states. The only state that does not set the IFLG bit is
PRELIMINARY
2
C clock line is released.
C8h
2
C, the Low period of the I
, then returns to the IDLE state. The I
2
C bus if:
2
C bus inputs SCLx. SDAx is
2
C block first transmits the
2
C enters MASTER mode
2
C bus clock line is
2
C completes the data
I
2
C Serial I/O Interface
2
C module
2
C
105