ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 200

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
ADDR[23:0]
DATA[7:0]
(output)
External Memory Write Timing
MREQ
Parameter
T
T
T
T
T
T
Note: *At the conclusion of a write cycle, deassertion of WR always occurs before any change to
1
2
3
4
5
6
CSx
X
WR
IN
ADDR, DATA, CSx, or MREQ.
Figure 41
Description
Clock Rise to ADDR Valid Delay
Clock Rise to ADDR Hold Time
Clock Rise to Output DATA Valid Delay
DATA Hold Time from Clock Rise
Clock Rise to CSx Assertion Delay
Clock Rise to CSx Deassertion Delay
and
T
7
T
T
Figure 41. External Memory Write Timing
3
1
T
Table 116
5
Table 116. External Write Timing
diagram the timing for external writes.
T
CLK
PRELIMINARY
T
9
T
10
T
T
T
4
2
T
6
8
Min.
1.6
5.0
3.0
3.0
—
—
Delay (ns)
AC Characteristics
Max.
10.2
10.2
10.5
9.7
—
—
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