ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 103

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
7
TX_DATA
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
7
RX_DATA
SPI Receive Buffer Register
The SPI Receive Buffer register (SPIx_RBR) is used by the SPI slave to receive
data from the serial bus. A write to the (SPIx_TSR) register initiates reception of
another byte, and only occurs in the master device. When the user reads the
SPIx_RBR register, a buffer is being read. The first SPIF bit must be cleared by
the time a second transfer of data from the shift register is initiated or an OVER-
RUN condition exists. Should an overrun occur, the byte causing the overrun is
lost.
The SPI Receive Buffer Read Only registers share the same address space as
the SPI Transmit Shift Write Only registers.
Value Description
00h–
FFh
Value Description
00h–
FFh
Table 42. SPI Receive Buffer Register
Table 41. SPI Transmit Shift Register
(SPI0_RBR = B8h, SPI1_RBR = BCh)
(SPI0_TSR = B8h, SPI1_TSR = BCh)
W
SPI data transmission.
SPI data reception.
X
X
R
7
7
W
X
X
R
6
6
PRELIMINARY
W
X
X
R
5
5
W
R
X
X
4
4
W
R
X
X
3
3
eZ80190 Product Specification
W
R
X
X
2
2
Serial Peripheral Interface
W
R
X
X
1
1
W
X
X
R
0
0
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