ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 101

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit
Position
7
IRQ_EN
6
5
SPI_EN
4
MASTER_EN
3
CPOL
2
CPHA
[1:0]
(SPIx_RBR), and SPI Transmit Shift register (SPIx_TSR), where the x in each
register name is either 0 or 1 depending on which UZI device the SPI is located
within. The SPI registers are described in this section.
SPI Control Register
The SPI Control Register, indicated in
serial peripheral interface.
Value Description
0
1
0
0
1
0
1
0
1
0
1
00b
(SPI0_CTL = B6h, SPI1_CTL = BAh)
R/W
The SPI system interrupt is disabled.
The SPI system interrupt is enabled.
Reserved—must be 0.
The SPI is disabled.
The SPI is enabled.
When enabled, the SPI operates as a slave.
When enabled, the SPI operates as a master.
The master SCK pin idles in a Low (0) state.
The master SCK pin idles in a High (1) state.
SS must go High after a transfer of every byte of data.
SS can remain Low to transfer any number of data bytes.
Reserved—must be 0.
7
0
Table 39. SPI Control Register
R
6
0
PRELIMINARY
R/W
5
0
Table
R/W
4
0
39, is used to control and set up the
R/W
3
0
eZ80190 Product Specification
R/W
2
1
Serial Peripheral Interface
R
1
0
R
0
0
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