ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 24

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Pin # Symbol
36
37
38
39
40
41
42
43
ADDR22 Address Bus
ADDR23 Address Bus
V
GND
DATA0
DATA1
DATA2
DATA3
DD
Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued)
Function
Power Supply
Ground
Data Bus
Data Bus
Data Bus
Data Bus
Signal Direction
Input/Output
Input/Output
Bidirectional,
tristate
Bidirectional,
tristate
Bidirectional,
tristate
Bidirectional,
tristate
PRELIMINARY
Description
The ADDR22 pin is configured as an output in
normal operation. The address bus selects a
location in memory or I/O space to be read or
written. This pin is configured as an input during
bus acknowledge cycles. Drives the Chip Select/
Wait State Generator block to generate Chip
Selects.
The ADDR23 pin is configured as an output in
normal operation. The address bus selects a
location in memory or I/O space to be read or
written. This pin is configured as an input during
bus acknowledge cycles. Drives the Chip Select/
Wait State Generator block to generate Chip
Selects.
Power Supply
Ground
The data bus transfers data to and from I/O and
memory devices. The eZ80190 device drives
these lines only during write cycles when the
eZ80190 device is the bus master. The data bus
is configured as an output in normal operation
and as an input during bus acknowledge cycles.
The data bus transfers data to and from I/O and
memory devices. The eZ80190 device drives
these lines only during write cycles when the
eZ80190 device is the bus master. The data bus
is configured as an output in normal operation
and as an input during bus acknowledge cycles.
The data bus transfers data to and from I/O and
memory devices. The eZ80190 device drives
these lines only during write cycles when the
eZ80190 device is the bus master. The data bus
is configured as an output in normal operation
and as an input during bus acknowledge cycles.
The data bus transfers data to and from I/O and
memory devices. The eZ80190 device drives
these lines only during write cycles when the
eZ80190 device is the bus master. The data bus
is configured as an output in normal operation
and as an input during bus acknowledge cycles.
Architectural Overview
10