ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 25

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Pin # Symbol
44
45
46
47
48
49
50
51
DATA4
DATA5
DATA6
DATA7
V
GND
NMI
HALT
DD
Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued)
Function
Data Bus
Data Bus
Data Bus
Data Bus
Power Supply
Ground
Nonmaskable
Interrupt
Halt
Signal Direction
Bidirectional,
tristate
Bidirectional,
tristate
Bidirectional,
tristate
Bidirectional,
tristate
Schmitt Trigger
Input, Active Low
Output, Active Low A Low on this pin indicates the CPU has stopped
PRELIMINARY
Description
The data bus transfers data to and from I/O and
memory devices. The eZ80190 device drives
these lines only during write cycles when the
eZ80190 device is the bus master. The data bus
is configured as an output in normal operation
and as an input during bus acknowledge cycles.
The data bus transfers data to and from I/O and
memory devices. The eZ80190 device drives
these lines only during write cycles when the
eZ80190 device is the bus master. The data bus
is configured as an output in normal operation
and as an input during bus acknowledge cycles.
The data bus transfers data to and from I/O and
memory devices. The eZ80190 device drives
these lines only during write cycles when the
eZ80190 device is the bus master. The data bus
is configured as an output in normal operation
and as an input during bus acknowledge cycles.
The data bus transfers data to and from I/O and
memory devices. The eZ80190 device drives
these lines only during write cycles when the
eZ80190 device is the bus master. The data bus
is configured as an output in normal operation
and as an input during bus acknowledge cycles.
Power Supply
Ground
The NMI input is prioritized higher than the
maskable interrupts. It is always recognized at the
end of an instruction, regardless of the state of
the interrupt enable control bits. This input
includes a Schmitt trigger to allow RC rise times.
This external NMI signal is combined with an
internal NMI signal generated from the WDT
block before being connected to the NMI input of
the CPU.
because a HALT instruction is executed.
Architectural Overview
11