ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 122

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Code
48h
50h
58h
60h
68h
70h
78h
80h
88h
90h
98h
A0h
A8h
B0h
B8h
C0h
C8h
D0h
D8h
F8h
Note:
If an illegal condition occurs on the I
code
be set and the IFLG bit cleared. The I
condition is transmitted on the I
I
The I2Cx_CCR register, indicated in
LSBs control the frequency at which the I
the I
2
C Clock Control Register
Status
Address + read bit transmitted, ACK not received
Data byte received in MASTER mode, ACK transmitted
Data byte received in MASTER mode, NACK transmitted
Slave address + write bit received, ACK transmitted
Arbitration lost in address as master, slave address + write bit received, ACK
transmitted
General Call address received, ACK transmitted
Arbitration lost in address as master, General Call address received, ACK
transmitted
Data byte received after slave address received, ACK transmitted
Data byte received after slave address received, NACK transmitted
Data byte received after General Call received, ACK transmitted
Data byte received after General Call received, NACK transmitted
STOP or repeated START condition received in SLAVE mode
Slave address + read bit received, ACK transmitted
Arbitration lost in address as master, slave address + read bit received, ACK
transmitted
Data byte transmitted in SLAVE mode, ACK received
Data byte transmitted in SLAVE mode, ACK not received
Last byte transmitted in SLAVE mode, ACK received
Second Address byte + write bit transmitted, ACK received
Second Address byte + write bit transmitted, ACK not received
No relevant status information, IFLG = 0
2
C clock line (SCL) when the I
00h
The STP and STA bits may be simultaneously set to 1 to recover from the
bus error. The I
). To recover from this state, the STP bit in the I2Cx_CTL register must
Table 54. I
2
C then sends a START.
2
C Status Codes (Continued)
PRELIMINARY
2
C bus.
2
C is operating in MASTER mode. The Write
2
Table
C bus, the bus error state is entered (status
2
C then returns to the IDLE state. No STOP
2
C bus is sampled and the frequency of
55, is a Write Only register. The seven
I
2
C Serial I/O Interface
108