ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 88

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
[7:6]
TRIG
[5:3]
1
CLRTXF
2
CLRRXF
0
FIFOEN
UART FIFO Control Registers
These registers, indicated in
FIFO pointers, and enable or disable the FIFO. The UARTx_FCTL registers share
the same I/O addresses as the UARTx_IIR registers.
Value
00
01
10
11
000b
0
1
0
1
0
1
(UART0_FCTL = C2h, UART1_FCTL = D2h)
Table 31. UART FIFO Control Registers
Description
The receive FIFO trigger level is set to 1. A receive data
interrupt is generated when there is 1 byte in the FIFO. This
bit is valid only if the FIFO is enabled.
The receive FIFO trigger level set to 4. The receive data
interrupt is generated when there are 4 bytes in the FIFO.
This bit is valid only if the FIFO is enabled.
The receive FIFO trigger level set to 8. The receive data
interrupt is generated when there are 8 bytes in the FIFO.
This bit is valid only if the FIFO is enabled.
The receive FIFO trigger level set to 14. The receive data
interrupt is generated when there are 14 bytes in the FIFO.
This bit is valid only if the FIFO is enabled.
Reserved—must be 000b.
This bit produces no effect.
This bit clears the transmit FIFO and resets the transmit FIFO
pointer. This bit is valid only if the FIFO is enabled.
This bit produces no effect.
This bit clears the receive FIFO, clears the receive error FIFO,
and resets the receive FIFO pointer. This bit is valid only if the
FIFO is enabled.
The transmit and receive FIFOs are disabled. The transmit
and receive buffers are only one byte deep.
The transmit and receive FIFOs are enabled.
W
7
0
W
6
0
PRELIMINARY
Table
W
5
0
31, are used to monitor trigger levels, clear
W
4
0
Universal Asynchronous Receiver/Transmitter
W
3
0
eZ80190 Product Specification
W
2
0
W
1
0
W
0
1
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