ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 70
ez80190
Manufacturer Part Number
ez80190
Description
Ez80190 Microprocessor
Manufacturer
ZiLOG Semiconductor
Datasheet
1.EZ80190.pdf
(222 pages)
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PS006613-0306
Bit
CS 0 Reset
CS 1 Reset
CS 2 Reset
CS 3 Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:5]
CS_WAIT
4
CS_IO
3
CS_EN
[2:0]
(CS0_CTL = AAh, CS1_CTL = ADh, CS2_CTL = B0h, CS3_CTL = B3h)
Chip Select x Control Register
The Chip Select x Control register, detailed in
specifies the type of Chip Select, and sets the number of WAIT states. The reset
state for the Chip Select 0 Control register is
other Chip Select control registers is
Value Description
000
001
010
011
100
101
110
111
0
1
0
1
000
Table 20. Chip Select x Control Register
R/W
0 WAIT states are inserted when this Chip Select is active.
1 WAIT state is inserted when this Chip Select is active.
2 WAIT states are inserted when this Chip Select is active.
3 WAIT states are inserted when this Chip Select is active.
4 WAIT states are inserted when this Chip Select is active.
5 WAIT states are inserted when this Chip Select is active.
6 WAIT states are inserted when this Chip Select is active.
7 WAIT states are inserted when this Chip Select is active.
An address match results in a Memory Chip Select.
An address match results in an I/O Chip Select.
Chip Select is disabled.
Chip Select is enabled.
Reserved—must be 000.
7
1
0
0
0
R/W
6
1
0
0
0
PRELIMINARY
R/W
5
1
0
0
0
00h
R/W
4
0
0
0
0
.
E8h
Table
R/W
3
1
0
0
0
eZ80190 Product Specification
, while the reset state for the 3
20, enables the Chip Selects,
R/W
2
0
0
0
0
Chip Selects and Wait States
R/W
1
0
0
0
0
R/W
0
0
0
0
0
56
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