ez80190 ZiLOG Semiconductor, ez80190 Datasheet - Page 109

• Manufacturer Part Number: ez80190
• Description: Ez80190 Microprocessor
• Manufacturer: ZiLOG Semiconductor

PS006613-0306
Operating Modes
the masters involved must send this repeated START condition or STOP condition
at the same position in the format frame. In other words, arbitration is not allowed
between:
•
•
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Clock Synchronization for Handshake
The Clock synchronizing mechanism can function as a handshake, enabling
receivers to cope with fast data transfers, on either a byte or bit level. The byte
level allows a device to receive a byte of data at a fast rate, but allows the device
more time to store the received byte or to prepare another byte for transmission.
Slaves hold the SCL line Low after reception and acknowledge the byte, forcing
the master into a WAIT state until the slave is ready for the next byte transfer in a
handshake procedure.
Master Transmit
In MASTER TRANSMIT mode, the I
receiver.
The device enters MASTER TRANSMIT mode by setting the Master Mode Start
bit (STA) bit in the I2Cx_CTL register to 1. The I
transmits a START condition when the bus is free. When a START condition is
transmitted, the IFLG bit is set to 1 and the status code in the I2Cx_SR register is
08h
either a 7-bit slave address or the first part of a 10-bit slave address, with the lsb
cleared to 0 to specify TRANSMIT mode. The IFLG bit should now be cleared to 0
to prompt the transfer to continue.
After the 7-bit slave address (or the first part of a 10-bit address) plus the write bit
are transmitted, the IFLG is set again. A number of status codes are possible in
the I2Cx_SR register.
A repeated START condition and a data bit
A STOP condition and a data bit
A repeated START condition and a STOP condition
. Before this interrupt is serviced, the I2Cx_DR register must be loaded with
PRELIMINARY
2
C transmits a number of bytes to a slave
2
C then tests the I
I
2
C Serial I/O Interface
2
C bus and
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