MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 83

• Manufacturer Part Number: MT90221
• Description: Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
• Manufacturer: Zarlink Semiconductor

MT90221
74
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
register operation
Reset Value (Hex):
Bit #
Bit #
Bit #
7:4
3:0
7:5
7:5
4
3
2
1
0
4
3
2
1
0
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
Unused. Should read 0’s.
Each bit set to ’1’ will enable the generation of the interrupt when the corresponding bit in
the IRQ IMA Group Overflow Status register is set. There is one bit for each status bit.
Unused. Should read 0’s.
This bit is set when the RX UTOPIA FIFO associated with an IMA Group overflows. This
bit is cleared by writing 0.
This bit is set when the counter for all cells associated with an IMA Group overflows.
(Input UTOPIA port). This bit is cleared by writing 0.
This bit is set when the counter for Idle Cells associated with an IMA Group overflows.
(Input UTOPIA port). This bit is cleared by writing 0.
This bit is set when the counter for Unassigned Cells associated with an IMA Group
overflows. (Input UTOPIA port). This bit is cleared by writing 0.
This bit is set when the counter for HEC Errored Cells associated with an IMA Group
overflows. (Input UTOPIA port). This bit is cleared by writing 0.
Unused. Should read 0’s.
This bit is set when the RX UTOPIA FIFO associated with a Link in UNI mode overflows.
This bit is cleared by writing 0.
This bit is set when the UTOPIA Input counter for all cells (or all Stuff cells event)
associated with a link used in UNI mode overflows. This bit is cleared by writing 0.
This bit is set when the UTOPIA Input counter for Idle Cells associated with a link used in
UNI mode overflows. This bit is cleared by writing 0.
This bit is set when the UTOPIA Input counter for Unassigned Cells associated with a link
used in UNI mode overflows. This bit is cleared by writing 0.
This bit is set when the UTOPIA Input counter for HEC Errored Cells associated with a
link used in UNI mode overflows. This bit is cleared by writing 0.
Table 101 - IRQ UTOPIA UNI Overflow Status Registers
204
00
210 - 213
1 register per IMA Group. The RxClk and TxClk signals must be active for correct
register operation
00
208 - 20B
1 register per link. The RxClk and TxClk signals must be active for correct
00
Table 99 - IRQ IMA Group Overflow Enable Register
Table 100 - IRQ IMA Overflow Status Registers
Description
Description
Description