MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 43

• Manufacturer Part Number: MT90221
• Description: Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
• Manufacturer: Zarlink Semiconductor

MT90221
bit of the Counter Transfer Command register. The
value ’0x001010’ enables the counter IRQ and
’xxx00010’ disables (masks) it.
6.2
The MT90221 can generate interrupts from many
sources. All interrupt sources can be enabled or
disabled. Write action is required to clear the source
of interrupt. Interrupts are grouped on a per link
basis, with six sub-categories for each link and two
special types for the IMA Group configuration. These
special interrupts are only present in the Link 0 IRQ
Status
representation of the interrupt register hierarchy.
6.2.1
There is a Master IRQ Status register that reports
interrupts generated by any event on any of the eight
links. Each bit of this register corresponds to a link. A
’1’ in a bit position indicates that the associated link
is reporting an interrupt condition. For each bit in the
34
Transfer
Interrupt Block
Frame
IRQ Master Status and IRQ Master Enable
Registers
Done
Pulse
register.
Handler Register
TX ICP Cell
Refer
RX FIFO Overflow
S
T
A
T
U
S
E
N
A
B
E
L
Link UNI Overflow Status
to
4 UTOPIA
READY BIT/ICP CELL TIME *
Counters
1 UTOPIA
Counters
Counters
4 RX
4 TX
Figure
IMA GRP CNTRS *
Figure 18 - IRQ Register Hierarchy
18
New RX ICP
S
T
A
T
U
S
for
1 set of registers
LODS
OVERFLOW
LCD
IMA Group
LIF
Link 3
IV
Registers
E
N
A
B
E
L
7
0
a
Group Counters
4 x IRQ
UTOPIA IMA
Link 2
Link
S
T
A
T
U
S
Link 1
S
T
A
T
U
S
Link 0
IRQ Master Status register, there is a corresponding
bit in the IRQ Master Enable register. When any IRQ
source is active and the corresponding Enable bit is
’1’, then the IRQ pin will go LOW (active).
The IRQ Master Status register always reports the
current state of the source(s) of interrupt. It does not
latch the interrupt request(s); it only reports that one
or more bit(s) in one or more IRQ Link Status
register(s) is (are) set.
The bits that are read as active (’1’ value) are
cleared when the source of the interrupt is cleared or
when the corresponding bit(s) in the IRQ Link
Enable register(s) is (are) set to 0. Writing to or
reading from the IRQ Master Status register has no
effect on the level of the interrupt pin.
6.2.2
Registers
There are four IRQ Link Status and four IRQ Link
Enable registers; one of each per link. The following
E
N
A
B
E
L
OVERFLOW
4 registers
IMA
S
T
A
T
U
S
IRQ Link Status and IRQ Link Enable
Link 0
Link 3
1 UTOPIA
RX FIFO Overflow
4 UTOPIA
Counters
Registers
1 x IRQ
Master
Note *: These 2 IRQ signals are
S
T
A
T
U
S
E
N
A
B
E
L
only present in IRQ Status
register for Link 0.
IRQ PIN