MT90221 Zarlink Semiconductor, MT90221 Datasheet
MT90221
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MT90221 Summary of contents
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This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ ...
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... RX External Static RAM Utopia I/F CTRL Utopia Level 2 BUS Utopia FiFo Processor I/F Figure 1 - MT90221 Block Diagram with Built-in IMA functions for 4 IMA Groups over links Quad IMA/UNI PHY Device DS5065 Ordering Information MT90221AL - +85 C • Provides Header Error Control (HEC) verifi ...
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... T1/E1 rates, the MT90221 device is compliant with the ATM FORUM IMA specifications for controlling IMA groups trunks in a single chip. The MT90221 can be configured to operate in different modes to facilitate the implementation of the IMA function at both CPE and Central Office sites. For ...
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... De-Scrambling and ATM Cell Filtering ..................................................................................................... 16 3.3 ATM Receive Path in IMA Mode .............................................................................................................. 16 3.3.1 ICP Cell Processor........................................................................................................................... 17 3.3.1.1 IMA Frame Synchronization...................................................................................................... 17 3.3.1.2 Link Information......................................................................................................................... 18 3.3.1.3 RX OAM Label .......................................................................................................................... 18 3.3.2 Out of IMA Frame (OIF) Condition ................................................................................................... 18 3.3.3 Link Out Of IMA Frame (LIF) Synchronization ................................................................................. 18 3.3.4 Filler Cell Handling ........................................................................................................................... 18 3.3.5 Stuff Cell Handling ........................................................................................................................... 18 3.3.6 Received ICP Cell Buffer .................................................................................................................. 18 Table of Contents MT90221 i ...
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... MT90221 3.3.7 Rate Recovery ................................................................................................................................. 19 3.3.8 Cell Buffer/RAM Controller............................................................................................................... 19 3.3.9 Cell Sequence Recovery ................................................................................................................. 19 3.3.10 Delay Between Links ....................................................................................................................... 20 3.3.10.1 RX Recombiner Delay Value .................................................................................................... 20 3.3.10.2 RX Maximum Operational Delay Value..................................................................................... 20 3.3.10.3 Link Out of Delay Synchronization (LODS)............................................................................... 20 3.3.10.4 Negative Delay Values.............................................................................................................. 21 3.3.10.5 Measured Delay Between Links................................................................................................ 21 3.3.10.6 Incrementing/Decrementing the Recombiner Delay ................................................................. 21 3.3.11 RX IMA Group Start-Up ................................................................................................................... 22 3 ...
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... RX ICP Cell Registers Description ........................................................................................................... 56 7.6 External SRAM Register Description ....................................................................................................... 58 7.7 RX Delay Registers Description ............................................................................................................... 60 7.8 RX Recombiner Registers Description ..................................................................................................... 63 7.9 TX/RX and PLL Control Registers Description......................................................................................... 65 7.10 Counter Registers Description ................................................................................................................ 70 7.11Interrupt Registers Description ................................................................................................................. 72 7.12 Miscellaneous Registers Description ...................................................................................................... 76 8.0 Application Notes......................................................................................................................................... 77 8.1 Connecting the MT90220 to Various T1/E1 Framers ............................................................................... 77 9.0 AC/DC Characteristics................................................................................................................................. 83 Table of Contents MT90221 iii ...
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... MT90221 Packaging Information........................................................................................................................................ 98 List of Changes.................................................................................................................................................. 100 List of Abbreviations and Acronyms............................................................................................................... 102 ATM Glossary .................................................................................................................................................... 102 iv Table of Contents ...
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... Figure 31 - External Memory Interface Timing - Write Cycle................................................................................ 91 Figure 32 - CPU Interface Timing - Read Access ................................................................................................ 93 Figure 33 - CPU Interface Motorola Timing - Write Access.................................................................................. 94 Figure 34 - CPU Interface Intel Timing - Write Access......................................................................................... 95 Figure 35 - JTAG Port Timing............................................................................................................................... 96 Figure 36 - System Clock and Reset.................................................................................................................... 97 Figure 37 - Metric Quad Flat Package - 208 Pin .................................................................................................. 98 List of Figures MT90221 v ...
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... MT90221 Pin Description ....................................................................................................................................................... 4 Pinout Summary ..................................................................................................................................................... 7 Table 1 - IDCR Integration Register Value ........................................................................................................... 12 Table 2 - ICP Cell Description .............................................................................................................................. 13 Table 3 - Cell Acquisition Time............................................................................................................................. 16 Table 4 - Differential Delay for Various Memory Configuration ............................................................................ 19 Table 5 - Conversion Factors Time/Cell (msec) ................................................................................................... 20 Table 6 - PCM Modes........................................................................................................................................... 24 Table 7 - PCM Clock and Mapping Options ......................................................................................................... 24 Table 8 - T1Channel Mapping Using 3 Channels Every 4 Channels ................................................................... 25 Table Channel Mapping Using 24 Consecutive Channels ...
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... Table Sync. Status Register................................................................................................................... 69 Table Sync. Status Register ................................................................................................................... 69 Table Clock Disabled Status................................................................................................................... 69 Table 89 - PLL REF Clock Disabled Status/Device Rev ..................................................................................... 70 Table 90 - Counter Byte Number 3 Register ....................................................................................................... 70 Table 91 - Counter Byte Number 2 Register ....................................................................................................... 70 Table 92 - Counter Byte Number 1 Register ....................................................................................................... 71 List of Tables MT90221 vii ...
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... MT90221 Table 93 - Select Counter Register ..................................................................................................................... 71 Table 94 - Counter Transfer Command Register ................................................................................................. 72 Table 95 - IRQ Master Status Register ................................................................................................................ 72 Table 96 - IRQ Master Enable Register .............................................................................................................. 73 Table 97 - IRQ Link Status Registers .................................................................................................................. 73 Table 98 - IRQ Link Enable Registers ................................................................................................................. 73 Table 99 - IRQ IMA Group Overflow Status Register.......................................................................................... 74 Table 100 - IRQ IMA Group Overflow Enable Register....................................................................................... 74 Table 101 - IRQ IMA Overflow Status Registers ...
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... UTOPIA Transmit Data Bus. Byte-wide data driven from ATM LAYER device to 24, 25, 26, [7:0] MT90221. Bit 7 is the MSB. All arriving data between the last byte of the previous 27, 28, 29 cell and the first byte of the following cell (indicated by the SOC signal) is ignored. ...
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... Transmit Address.Five bit wide true data driven from the ATM to the PHY layer to 37, 38 [4:0] poll and select the appropriate MT90221. TxAddr[4] is the MSB. Each MT90221 keeps its addresses. The value for the Tx and Rx portions of the MT90221 can be different ATM Output Port Signals (UTOPIA Receive Interface) (see Note 1) 205, 206, RxData O UTOPIA Receive Data Bus ...
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... I Processor Chip Select. This is an active low input signal. If this signal is high, the MT90221 ignores all other signals on its processor bus. If this signal is low, the MT90221 accepts the signals on its processor bus. De-asserting this signal to high will terminate an access cycle. ...
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... Receive line 8KHz Frame Pulse 3-0. This signal represents the 8 KHz reference 144, 150 [3:0] received from the incoming line. The MT90221 can be programmed to accept different 8 KHz pulse formats at this input. 1. For ST-BUS applications low going pulse (F0), which delimits the 32 channel frame of ST-BUS interface at DSTi and DSTo lines. See STBUS timing diagram for this sync pulse ...
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... NC No Connect. Can be left unconnected. 97, 120, 122, 129, 131 74 Clk I System Clock (25 MHz nominal). In the MT90221, this clock is used for all internal operations of the device. 76 Test1 I Test1. This signal should be pulled up for normal operation. 54 Reset I System Reset. This is an active low input signal. It causes the device to enter the initial state ...
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... The addition, removal or restoration of a link is controlled by software using the various control registers in the MT90221 and in the framers. Decisions are based on the MT90221 and framers status registers. 1.1.4 The MT90221 provides numerous registers and counters to implement a polling and/or interrupt mechanism for tracking link and IMA Group status. This traffi ...
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... Static RAM • various performance monitoring counters • 8-bit microprocessor interface (adaptable to Intel or Motorola interfaces) The MT90221 can be separated into four major independent blocks and three support blocks. The four major independent blocks are: • the ATM Transmit Path • the ATM Receive Path • ...
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... UNI Filler cell (in IMA mode) to the line. The default values for the Idle and the Filler cells comply with the ATM IMA Specification and are pre- loaded in the MT90221 following a reset. The TX Cell RAM Control register can be used to re- initialize the TX Cell RAM. ...
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... Idle Cell used in UNI mode The remaining 58 cells can be assigned to any of the 12 TX FIFOs. The TX FIFOs are divided UTOPIA FIFOs and 4 TX Link FIFOs.The MT90221 implements one TX UTOPIA FIFO for each link when used in UNI and one for each IMA Group for a total UTOPIA FIFOs ...
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... ICP Cell Generator Once per IMA frame, an ICP cell is transmitted on each link of the IMA Group. The content of the ICP cell is controlled both by MT90221 and software. The software content of the ICP cell bytes is stored in buffer RAM. A copy of the ICP cell for each group is kept in the internal Transmitter Cell RAM ...
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... ICP cell into the internal Cell RAM area and to start using this new ICP cell. The MT90221 uses a flag (status bit) to indicate that this transfer is underway. Changes should not be made to the content of the ICP cell in the buffer area until the transfer to the internal memory is complete ...
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... IMA Group. LID should not be changed when a group is operational. Ensure each link that is part of an IMA group has a unique LID (note that the MT90221 does not verify LIDs). • Write the ICP Cell Offset value to TX ICP Cell Offset registers. This value depends on the value of M ...
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... SYNC state occurs after “ ” cells (DELTA in ITU I.432) are correctly received. In the SYNC state, the CD circuit treats the incoming ATM cell stream as stable and the MT90221 functions normally. While in the SYNC state incorrect HEC is obtained “a” consecutive times (ALPHA in ITU I.432), cell delineation is considered lost and a transition is made back to the HUNT state (see Figure 6) ...
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... Incoming Idle and Unassigned cells can be detected and dropped automatically. 3.3 ATM Receive Path in IMA Mode The block diagram at Figure 7 illustrates the MT90221 IMA mode receive path. The receiver must rearrange the incoming bit streams from N-links ( into a single UTOPIA cell stream. ALPHA ...
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... Cell RXSYNC S/P Delineation DSTi [3] Figure 7 - The MT90221 Receiver Circuit in IMA Mode 3.3.1 ICP Cell Processor In IMA mode, the transmitter inserts special ICP cells in the various outgoing streams every M ATM cells to comply with the IMA specification. The receive block is using these ICP cells to synchronize with the Far End transmit side and to reconstruct the ATM cell original sequence ...
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... LIF status bit to determine when the condition is cleared. 3.3.4 Filler Cell Handling The MT90221 scans each incoming cell received for the Filler Cell Indication code. Filler cells are written to external RAM to keep the IMA frame aligned. They are automatically discarded after being read from the external RAM by the recombiner ...
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... The storage unit keeps the last read ICP cell and has room for up to three new ICP cells. 3.3.7 Rate Recovery The MT90221 computes the internal RX IMA Data Cell Rate (IDCR) for each IMA Group. The cell rate of the reference ...
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... Cell Delay Variation (CDV). To provide an optimal recombiner delay, the MT90221 adds a guardband delay to the current worst case recombination delay when the IMA Group is first started up. Guardband delay is programmable and minimizes the number of disruptions that would otherwise occur in accommodating link delays exceeding the current worst case ...
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... Guardband/Delta Delay register and then a command to increase the delay is issued (using the Increment/Decrement Delay Control register). The MT90221 device stops the recombiner process for the amount of time specified and then resumes the recombiner process. No cells are lost but there is an effect on the CDV. The increment ...
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... After 3.4 The ATM Receive Path in UNI Up to four incoming T1/E1 lines can be connected to the MT90221 receiver and forwarded to the UTOPIA L2 interface served by an external ATM-Layer device in UNI Mode. Figure 8 illustrates four of the eight possible UTOPIA ports that can be addressed through the UTOPIA Interface. ...
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... Transmit PCM blocks are independent from the Receive PCM blocks. The TX port of a framer can be connected to any of the MT90221 TX UTOPIA Input ports and the RX port of a framer can be connected to any of the MT90221 RX UTOPIA Output ports. 4.1 Serial to Parallel (S/P) and Parallel to Serial (P/S) Converters Each T1/E1 link has a S/P and P/S unit assigned ...
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... MT90221 PCM Major Modes TX PCM Control Registers 1 & 2 Reg 1 bit 6 Mode 1 0 Mode 2 0 Mode 3 1 Mode 4 1 Mode 5 0 Mode 6 0 Mode 7 1 Mode 8 1 PCM Mode Clock Frequency Mapping Grouped T1 ISDN Yes (23 channels) T1 Clear Channel Yes (24 channels) E1 (30 channels " ...
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... TX PCM Link Control register number 2 and can be any of the four RXCK or four external REFCK clocks. As there is no PLL inside the MT90221, the source frequency has valid ST- BUS Clock signal (i.e., 4.096 MHz). The TXSYNC signal is generated by the MT90221 and meets the ST-BUS format ...
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... Detailed ST-BUS Grouped Mapping (24 Consecutive Channels) In this option, the 24 bytes of serial voice/data channels of the DS-1 use the first 24 consecutive channels over the 32 ST-BUS channels. The MT90221 tri-states the DSTo lines for the unused channels (25 - 31). Refer to Table 9. 4.2.1.3 Detailed ST-BUS ISDN Mapping (T1 ISDN Modes) When the T1 ISDN modes are selected, channel 24 is not used to carry bytes from ATM cells ...
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... MT90221 to operate with the majority of available off-the-shelf T1 framers. When operating in the generic PCM system Interface at 1.544 MHz, the MT90221 does not use the first bit of the PCM frame (i.e., the T1 framing bit) to perform the G.804 recommended transmission convergence function (see Figure 12). This frame bit is also ignored on the receive side ...
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... The edge of the RXCK and TXCK signals that is used to sample the incoming, and transmit the outgoing, data is fully programmable on a per link basis. This allows the MT90221 to operate with the majority of off-the-shelf E1 framers. The MT90221 does not use timeslots 0 and 16 to perform the G.804 transmission function (see Figure 13) ...
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... Figure 14 - TXCK and TXSYNC Output Pin Source Options Channel 0 bit 7 Channel 0 bit 0 ... Unused or Unused or ... High Impedance High Impedance ... ... ... ... Channel 16 bit 7 Channel 16 bit 0 ... Unused or Unused or ... High Impedance High Impedance ... ... ... ... Cell Delineation P/S MT90221 ... Channel 1 bit 7 ... Bit Cell ... ... ... ... Channel 17 bit 7 ... Bit Cell ... ... ... ... DSTi RXCK S/P RXSYNC TXSYNC DSTo TXCK PLLREF0 PLLREF1 29 ...
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... Clock source activity can be verified using the Clock Activity register as described in 4.3.4 Verification of Clock Activity. 5.0 UTOPIA Interface Operation The MT90221 supports the UTOPIA L2 Mode for cell level handshake only. Each port can be assigned an address ranging from 0 to 30. The address value reserved and should not be used for any MT90221 port ...
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... HEC counter is not incremented. 5.2 ATM Output Port The MT90221 supports a 53 byte cell stream via the ATM output port. Cells received at the ATM output port are stored in the RX UTOPIA FIFO before being processed by the UTOPIA Interface. The output of the UTOPIA Interface can be stopped by the ATM Layer device by de-asserting the RxENB* signal ...
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... RX UTOPIA FIFO. 5.6 UTOPIA Operation in IMA Mode In IMA mode eight MT90221s, with up to four UTOPIA ports each (one port per IMA Group), can be served by an external UTOPIA L2 ATM-Layer device. This provides different logical IMA- channels ...
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... ATM Layer Device Figure 17 - ATM Mixed-Mode Interface to One MT90221 6.0 Support Blocks 6.1 Counter Block The MT90221 includes 64 24-bit counters to provide statistical information on the device’s operation. All the counters are cleared by a hardware reset. A maskable interrupt can be generated when the counter overflows. ...
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... IRQ and ’xxx00010’ disables (masks) it. 6.2 Interrupt Block The MT90221 can generate interrupts from many sources. All interrupt sources can be enabled or disabled. Write action is required to clear the source of interrupt. Interrupts are grouped on a per link basis, with six sub-categories for each link and two special types for the IMA Group confi ...
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... The Ready bit is set to 1 when the transfer is complete. Bit latched bit in the IRQ Link 0 Status register and is cleared by overwriting it with 0. Each of these two interrupt sources can be masked by writing a ’1’ to the bit corresponding to the interrupt source in the IRQ Link 0 Enable register. MT90221 interrupt sources are enabled 35 ...
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... RX UTOPIA FIFO associated with an IMA Group. This is the RX UTOPIA IMA Group FIFO Overflow Enable register. 6.3 Register and Memory Map 6.3.1 Access to the Various Registers Since the MT90221 and microprocessor operate from two different clock sources, access to a MT90221 register is asynchronous. synchronized ...
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... Direct Access Direct access registers can be written or read directly by the microprocessor, without having to use otherregisters. Upon a write access to the MT90221 internal registers, the data is stored in an internal latch and transferred to the destination register within 2.5 system clock cycles (100 nsec at 25 MHz). ...
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... MT90221 7.0 Register Descriptions Reset Address Access (Hex) Type 000 - 003 D 008 - 00B D 00C D 00D D 00E D 040 - 043 D 048 - 04B D 04C D 04D D 205 D 221 D 140 D 150 D 14A D 14B D 14C D 14D D 14E D 14F D 0C0 - 0C3 D 0DD - 0E0 D 0C4 - 0C7 D 200 - 203 D 0CC - 0CF ...
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... RX Reference Link Control Registers 79 RX IDCR Integration Register 80 TX PCM Link Control Register # PCM Link Control Register # PCM Link Control Register 83 PLL Reference Control register 84 Clock Activity Register 85 RX Sync. Status Register 86 TX Sync. Status Register Table 11 - Register Summary MT90221 Description 39 ...
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... MT90221 Reset Address Access (Hex) Type 09C D 09D D 214 S 215 S 216 S 217 S 207 S 232 D 218 D 222 - 225 D 219 - 21C D 235 D 204 D 210 - 213 D 208 - 20B D 22A - 22D D 206 D 04E D 0DA D 400, 440 D 480, 4C0 D 500, 540 D 580, 5C0 D 40 Value Table # ...
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... Enable UTOPIA PHY address of link enables the PHY port Address. UNI mode. 1 R/W Enable UTOPIA PHY address of link enables the PHY port Address. UNI mode. 0 R/W Enable UTOPIA PHY address of link enables the PHY port Address. UNI mode. Table 14 - UTOPIA Input Link PHY Enable Register Description Description Description MT90221 41 ...
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... MT90221 Address (Hex): 00D Direct access 1 register to enable the IMA Groups. The TxClk signal must be active for correct register operation Reset Value (Hex): 00 Bit # Type 7-4 R/W Reserved. Write all 0’ R/W Enable UTOPIA PHY address of IMA Group enables the PHY port Address. ...
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... Enable UTOPIA PHY address of IMA Group enables the PHY port Address. 1 R/W Enable UTOPIA PHY address of IMA Group enables the PHY port Address. 0 R/W Enable UTOPIA PHY address of IMA Group enables the PHY port Address. Table 20 - UTOPIA Output Group PHY Enable Register Description Description Description MT90221 43 ...
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... MT90221 Address (Hex): 205 Direct access 1 register to enable interrupts from IMA Groups. The RxClk signal must be active for correct register operation Reset Value (Hex): 00 Bit # Type 7-4 R Unused. Read all 0’s. 3 R/W When set to 1, the corresponding bit in the Overflow Status register can generate an interrupt ...
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... Table FIFO Length Definition Register 1 Address (Hex): 14B Direct access Reset Value (Hex): 33 Bit # Type 7:4 R/W TX FIFO Length Link 3. 3:0 R/W TX FIFO Length Link 2. Table FIFO Length Definition Register 2 Description Table Cell RAM Control Register Description Table UTOPIA FIFO Level Register Description Description MT90221 45 ...
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... MT90221 Address (Hex): 14C Direct access Reset Value (Hex): 33 Bit # Type 7:0 R/W Reserved. Write 0 for normal operation. Table FIFO Length Definition Register 3 Address (Hex): 14D Direct access Reset Value (Hex): 33 Bit # Type 7:0 R/W Reserved. Write 0 for normal operation. Table FIFO Length Definition Register 4 ...
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... Defines the ICP cell offset of link N. The value of M determines which significant bits are used as follows: M=256; bits 7-0 are used, M=128; bits 6-0 are used; M=64; bits 5-0 are used; M=32; bits 4-0 are used. Description Description Table Link ID Registers Description Table ICP Cell Offset Registers MT90221 47 ...
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... MT90221 Address (Hex): 200 - 203 Direct access 1 register per TX IMA Group Reset Value (Hex): 05 Bit # Type 7:4 R Unused. Read all 0’s. 3-0 R/W Defines the integration period for an IMA Group: 1111: Reserved. Do not use. 1110: 2 1101: 2 1100: 2 1011: 2 1010: 2 1001: 2 1000: 2 0111: 2 0110: 2 0101: 2 ...
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... Link 3 is not in IMA mode means Link 2 is not in IMA mode means Link 1 is not in IMA mode means Link 0 is not in IMA mode. Description Table IMA Control Registers Description Table IMA Mode Status Register MT90221 49 ...
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... MT90221 7.3 TX ICP Register Description Tables describe the TX ICP registers. Address (Hex): 148 Direct access Controls the transfer of TX ICP cells and frame pulse indication Reset Value (Hex): 0F Bit # Type 7 R/W When 1 indicates the end of a frame was detected in IMA Group #3. Cleared by writing 0. ...
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... R/W HEC is always calculated and inserted by the MT90221 R/W OAM, should be set to 0x01 7 06 R/W Cell ID, Link ID. The bit 7 (Cell ID) is controlled by the MT90221, the Link ID is provided by the TX Link ID Register R/W IMA Frame Sequence Number. Inserted by the MT90221 R/W ICP Cell Offset. Inserted by the MT90221 based on the Link Offset register info ...
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... MT90221 7.4 RX Registers Description Tables describe the Receive registers. Address (Hex): 100 -103 Direct access 1 register per link Reset Value (Hex): 0C Bit # Type 7 R/W A Value of 0 select to count the number of Stuff cells received by the physical link. A value of 1 selects to count the total number of cells received by the link. ...
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... An OIF state was detected on the physical link 2. Cleared by writing R/W An OIF state was detected on the physical link 1. Cleared by writing R/W An OIF state was detected on the physical link 0. Cleared by writing a 0. Description Description Table OAM Label Register Description Table OIF Status Register MT90221 53 ...
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... MT90221 Address (Hex): 116 Direct access 1 register for the 4 RX links Reset Value (Hex): 00 Bit # Type 7-4 R/W Reserved. Write 0 for normal operation. 3 R/W Write clear the OIF counter for physical link 3. 2 R/W Write clear the OIF counter for physical link 2. 1 R/W Write clear the OIF counter for physical link 1. ...
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... The value is updated on completion of the write action in the RX Load Values register Reset Value (Hex): 00 Bit # Type 7:0 R Content of the OIF counter for the link selected in the RX Load Values/Link Select register. Table Link OIF Counter Value Register Description Table ICP Cell Offset Register Description Description Description MT90221 55 ...
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... MT90221 Address (Hex): 11D Direct access The value is updated on completion of the write action in the RX Load Values register Reset Value (Hex): 20 Bit # Type 7 R LIF state of the link selected in the RX Load Values/Link Select register LCD state of the link selected in the RX Load Values/Link Select register. ...
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... These 2 bits select the type of cells stored in the RX ICP Cell buffer for physical link 0. 00: valid RX ICP Cells with changes. 01: All valid RX ICP Cells. 10: All valid RX Cells. 11: No cell written into RX buffer. Table ICP Cell Type RAM Register 1 Description MT90221 57 ...
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... MT90221 Address (Hex): 1C6 Direct access 1 reg. for all 4 RX link FIFO Reset Value (Hex): 00 Bit # Type 7-4 R/W Reserved. Write 0 for normal operation value of 1 will increment the position of the read pointer for the physical link has no effect value of 1 will increment the position of the read pointer for the physical link has no effect ...
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... Address (Hex): 291 Synchronized access Set address before the transfer is initiated with the RX External SRAM Control register Reset Value (Hex): 00 Bit # Type 7:0 R/W RX External SRAM Read/Write Address bit 7:0. Table External SRAM Read/Write Address 0 Description Table 60 - SRAM Control Register Description Description MT90221 59 ...
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... MT90221 Address (Hex): 290 Synchronized access Set address before the transfer is initiated with the RX External SRAM Control register Reset Value (Hex): 00 Bit # Type 7:0 R/W RX External SRAM Read/Write Address bit 15:8. Table External SRAM Read/Write Address 1 Address (Hex): 28F Synchronized access Set address before the transfer is initiated with the RX External SRAM Control ...
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... Upon a write to this register, the bit will and will return to 1 when the transfer is completed 6 R Toggle Bit. 5 R/W Write 0 to initiate a transfer from the MT90221 registers to the external RAM. Write 1 to initiate a transfer from the external RAM to the MT90221 registers. 4 R/W Reserved, write 0 for normal operation. 3 R/W When Test Mode bit is 1 ...
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... MT90221 Address (Hex): 29D Direct access Used to initiate an update of the RX Delay registers based on the link and delay value to read Reset Value (Hex): 00 Bit # Type 7:6 R/W 00: normal delay, 01: read pointer, 10: write pointer. 5 R/W Writing a 1 will reset the value of the maximum delay over time register for the selected IMA Group (see bits 1:0) ...
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... Direct access 1 reg. per IMA Group (value in number of cells) Reset Value (Hex): 00 Bit # Type 7:6 R/W Unused. Read 0 after reset. 5:0 R/W MSB of the Maximum Operational Delay value Bits 13:8. Table Maximum Operational Delay MSB Register Description Description Description Description Description MT90221 63 ...
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... MT90221 7.8 RX Recombiner Registers Description Tables describe the RX Recombiner registers. Address (Hex): 180 - 183 Direct access 1 register per RX link Reset Value (Hex): 00 Bit # Type 7:3 R Unused. Read all 0’s. 2 R/W Recombiner Control enable the recombiner and disable. This bit works in conjunction with the RX Recombiner Delay register. ...
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... channels) 15 1000: 2 clock cycles 14 0111: 2 clock cycles 13 0110: 2 clock cycles 12 0101: 2 clock cycles 11 0100: 2 clock cycles 10 0011: 2 clock cycles 09 0010: 2 clock cycles 08 0001: 2 clock cycles 07 0000: 2 clock cycles Table IDCR Integration Registers Description Description MT90221 65 ...
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... MT90221 7.9 TX/RX and PLL Control Registers Description Tables describe the TX/RX and PLL Control registers. Address (Hex): 080 - 083 Direct access 1 reg. per TX link Reset Value (Hex): 00 Bit # Type 7:5 R Unused. Read all 0’s. 4 R/W TXCK and TXSYNC Direction: When the bit is 0 (default value) ...
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... RX Clock polarity: Falling edge is used to sample data at DST if bit is 1. Rising edge of RXCK is used to sample data at DSTi if bit is 0. Valid in Generic PCM mode only 0 R/W RX frame pulse polarity. Positive if bit is 1. Negative if bit is 0. Valid in Generic PCM mode only. Table PCM Link Control Register Description Description MT90221 67 ...
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... MT90221 Address (Hex): 098 Direct access Reset Value (Hex): 00 Bit # Type 7 R/W Writing a 1 forces the deselecting of the selected clock when it failed. 6:5 R/W Reserved. Set to 0 for normal operation. 4:3 R/W These 2 bits are used to select the source for the signal at PLLREF1: The valid combinations are: ...
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... A ’1’ signifies that the PLLREF1 Clock is disabled ’1’ signifies that the PLLREF0 Clock is disabled. Table 88 - PLL REF Clock Disabled Status/Device Rev Description Table Sync. Status Register Description Table Sync. Status Register Description Table Clock Disabled Status Description MT90221 69 ...
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... MT90221 7.10 Counter Registers Description Tables describe the Counter registers Address (Hex): 214 Synchronized access The value in this register is used for internal access to the counter when the transfer command is issued Reset Value (Hex): 00 Bit # Type 7:0 R/W A read accesses the MSB (byte 3) of the Counter selected in the Select Counter register. ...
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... R/W 00: Reserved. Do not use. 01: initiate a read or write of the counter value. 10: initiate a read or write of the IRQ enable counter bit. 11: not used. Table 93 - Counter Transfer Command Register Description Table 92 - Select Counter Register Description MT90221 71 ...
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... MT90221 7.11 Interrupt Registers Description Tables 94 to 102 describe the Interrupt registers. Address (Hex): 232 Direct access Reset Value (Hex): 00 Bit # Type 7:4 R Reserved. 3:0 R Each bit represents a link. A ’1’ means that the corresponding link has a valid request for interrupt. The level of the IRQ pin is controlled by the bits in this register and the corresponding bits in the IRQ Master Enable Register ...
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... There is one bit for each IMA Group. A bit is set when one or more of the 4 counters or the RX UTOPIA FIFO associated with an IMA Group overflows. Table 98 - IRQ IMA Group Overflow Status Register Description Table 96 - IRQ Link Status Registers Description Table 97 - IRQ Link Enable Registers Description MT90221 73 ...
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... MT90221 Address (Hex): 204 Direct access Reset Value (Hex): 00 Bit # Type 7:4 R Unused. Should read 0’s. 3:0 R/W Each bit set to ’1’ will enable the generation of the interrupt when the corresponding bit in the IRQ IMA Group Overflow Status register is set. There is one bit for each status bit. ...
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... This bit is set when the RX PCM Link counter for HEC Errored Cells associated with a link overflows. 0 R/W This bit is set when the RX PCM Link counter for bad ICP Cells associated with a link overflows. Table 102 - IRQ Link UNI Overflow Status Registers Description MT90221 75 ...
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... MT90221 7.12 Miscellaneous Registers Description Tables 103 to 105 describe the General Status and Test Register. Address (Hex): 206 Direct access Reset Value (Hex): 10 Bit # Type 7:4 R Device Revision Number: reads 0001. 3 R/W Set when the UTOPIA output clock is missing or too slow. This latched bit is cleared by writing a 0 ...
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... ATM cells in a round-robin fashion and sends them over grouped T1/E1 lines in a logical connection (on public or private networks) and recombines the cells to recover the original high- bandwidth stream at the receiving end. Zarlink's MT90221 is ideally suited to implement the IMA function. 8.1 Connecting the MT90221 to Various T1/E1 Framers ...
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... MT90221 UTOPIA BUS DSTo[0:3 DSTi[0:3] ATM LAYER BUS MT90221 DEVICE TXCK[0-3] RXCK[0-3] TXSYNC[0-3] RXSYNC[0-3] Clock Recovery and Dejitter Figure 19 - PCM MODE 2 AND 4: Synchronous ST-BUS Mode (Using ST-BUS/2.048 Mbps Backplane Compatible Framers) 78 TDM Back-Plane ST-BUS (ST-BUS) I/F DATA Data Lines ST-BUS I/F DATA ...
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... RXSYNC[3] TXSYNC[3] TXCK[3] DSTo[3] Note: The MT9074 #1 is configured in Line Sync. mode and all other MT9074s are configured in Bus Master mode. Figure 20 - PCM MODE 2 and 4 CTC Mode (Using MT9074 T1/E1 Single Chip Transceivers) MT90221 MT9074/#1 DSTo C4b F0b DSTi 20 MHz +/-50 PPM MT9074#N ...
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... MT90221 RXCK[0] RXSYNC[0] TXSYNC[0] TXCK[0] DSTo[0] UTOPIA MT90221 LEVEL 2 DEVICE BUS RXCK[3] RXSYNC[3] TXSYNC[3] TXCK[3] DSTo[3] Note: All MT9074 are configured in Line Sync. mode (Using Zarlink MT9074 T1/E1 Single Chip Transceivers) 80 DSTi[0] DSTi[3] Figure 21 - PCM MODE 2 AND 4: ITC Mode MT9074 DSTo C4b ...
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... Applications with Asynchronous Lines) PCM Data 1.544 or 2.048 MHz 8 kHz [T0] 1.544 or 2.048 MHz 8 kHz [R0] PCM Data PCM Data 1.544 or 2.048 MHz 8 kHz [T3] 1.544 or 2.048 MHz 8 kHz [R3] External Source MT90221 T1/E1 Legacy Trunks Framers at 1 Mbps Legacy Trunks T1/ Mbps Framers Legacy Trunks at 1 Mbps T1/E1 Framers 81 ...
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... MT90221 8.2 Optimum Usage of 1 Bank of Memory with a 4 Port Device Due to the addressing mode of the MT90221, only half of the memory locations are utilized when operating in IMA mode. This is mainly due to the fact that only links can be used. With some external circuitry, the addressing can be altered to gain access to the unused half of the memory that would correspond to the links ...
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... 115 222 2 0 MT90221 Min Max V -0.3 3 -1 -40 125 ST Max Units Test Conditions 85 ˚C 3.6 V Test Conditions System Clock 25 MHz. PCM clock @ 2.048MHz ...
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... MT90221 DC Electrical Characteristics* - Characteristics 13 Output Low Current 14 Output Pin Capacitance 15 High Impedance Leakage * DC Electrical Characteristics are over recommended temperature and supply voltage ‡ Typical figures are =3.3V, and for design aid only: not guaranteed and not subject to production testing DD AC Electrical Characteristics ...
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... PCM Bit Bit Cell Stream TXSYNC 0-3/ RXSYNC 0-3 TXCK 0-3/ RXCK 0-3 DSTi0-3 DSTo0-3 Figure 25 - ST-BUS Timing Diagram Bit Cell t FPH t FPS t t SIH t SIS t SOD MT90221 Bit Cell 4W t 4cyc ...
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... MT90221 AC Electrical Characteristics Characteristic 1 TXCK/RXCK Clock period for T1, 1.544 MHz mode for E1, 2.048 MHz mode 2 TXCK/RXCK Clock Width High or Low for T1, 1.544 MHz mode for E1, 2.048 MHz mode 3 Frame Pulse Setup 4 Frame Pulse hold 5 DSTi 0-3 Serial Input Setup 6 DSTi 0-3 Serial Input Hold ...
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... I t FPD t t FPH FPS t SIH t SIS t FPS I t FPSH t FPD MT90221 Positive Polarity Selected CYC Bit Sampled With Falling Edge Positive Polarity Selected CYC Bit Transmitted With Rising Edge Negative Polarity Selected Rising Edge Bit Sampled With Negative Polarity Selected ...
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... MT90221 AC Electrical Characteristics - Utopia Interface Transmit Timing Signal name TxClk TxData[7:0], TxSOC, TxEnb*, TxAddr[4:0] TxClav[0] AC Electrical Characteristics - Receive Timing Signal name RxClk RxEnb*, RxAddr[4:0] RxData[7:0], RxSOC, RxClav[0] Note 1 - The RXCLK signal needs to be synchronous with the system clock refer to paragraph 5.2. 88 DIR ...
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... Figure 28 - Setup and Hold Time Definition Clock Signal Valid Signal tT11 Signal Going Low Impedance From Clock Figure 29 - Tri-State Timing tT6, tT8 Input Hold From Clock Signal Going High Impedance t 1 T10 tT12 Signal Going High Impedance From Clock MT90221 89 ...
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... MT90221 AC Electrical Characteristics - External Memory Interface Timing - Read Access Item Description t MT90220 System Clock Period CLK t Read Cycle Time RC t Address Setup Time AVRS t Address Hold Time AVRH t Chip Select Setup Time CSRS t Chip Select Hold Time CSRH t Write Enable* Setup Time ...
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... Note: The SR_WE signal stays LOW until a READ cycle performed Figure 31 - External Memory Interface Timing - Write Cycle Min clk t avws Address Valid csws t wews t wds Data Valid MT90221 Typ Max -10 ns CLK avwh t cswh t wewh t wdh 91 ...
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... MT90221 pre-load register on the rising edge of the UP_CS* signal. In Intel timing mode, the data is clocked into MT90221 pre-load register on the rising edge of the UP_R/W* signal. Right after that transition, the data is transferred to the MT90221’s internal register. ...
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... UP_D low impedance after falling edge of UP_OE UP_OE UP_CS t ws UP_R/W UP_AD[9:0] UP_D[7:0] Figure 32 - CPU Interface Timing - Read Access Sym Min Typ Max ACC 2 Address Valid t oe Data Valid t acc MT90221 Units Test Conditions ...
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... MT90221 AC Electrical Characteristics - CPU Interface Motorola Timing - Write Cycle Characteristics 1 UP_R/W* set-up time to UP_CS* falling edge 2 Address and Data set up before rising edge of UP_CS* 3 UP_AD and Data hold time after UP_CS rising edge 4 UP_R/W low after rising edge or UP_CS 5 UP_CS* high before next UP_CS low Note 1 - For internal synchronization purposes, 2 system clock cycles are required between a write access and the next valid access ...
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... UP_A[9:0] UP_D[7:0] Figure 34 - CPU Interface Intel Timing - Write Access Sym Min Typ Max ADH t 1 CSH (see Note 1) t adh ADDRESS VALID t su DATA VALID MT90221 Units Test Conditions cycle system clock t csh ...
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... MT90221 AC Electrical Characteristics - JTAG Port and RESET Pin Timing Parameter TCK period width TCK period width LOW TCK period width HIGH TDI setup time to TCK rising TDI hold time after TCK rising TMS setup time to TCK rising TMS hold time after TCK rising ...
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... RESET pulse width CLK RESET Symbol Min Typ TCLK t 20 TCLKL t 20 TDKH t CLKR t CLKF t 10 RST t t clkrl clklf t rst Figure 36 - System Clock and Reset MT90221 Max Units Test Conditions Clk period t tclk t t tclkl tclkh 97 ...
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... MT90221 Pin # Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) JEDEC Standard 2.6mm Footprint MS-29 5) MQFP-208 Package complies to JEDEC Standard MS- See Detail A C1 Figure 37 - Metric Quad Flat Package - 208 Pin ...
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... Metric Quad Flat Package Dimensions 208-Pin Min 0.01 (0.25) .126 (3.20) .007 (0.18) .007 (0.18) .003 (0.076) .003 (0.076) 1.197 (30.40) 1.098 (27.90) .020 BSC (0.5 BSC) 1.197 (30.40) 1.098 (27.90) .018 (0.45) .051 REF (1.30 REF MT90221 Max .161 (4.10) .142 (3.60) .011 (0.28) .009 (0.28) .008 (0.20) .006 (0.152) 1.212 (30.80) 1.106 (28.10) 1.212 (30.80) 1.106 (28.10) .030 (10.76 ...
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... MT90221 List of Changes Page Numbers Newer Older ...
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... With: “1 ” 2nd line of table “2 ” With: “1 ” 2nd line of table “10” With: “5” “10” With: “5” “10 CLK period” With: “10” “ns” With: “clk period” MT90221 101 ...
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... MT90221 List of Abbreviations and Acronyms AAL ATM Adaptation Layer ATM Asynchronous Transfer Mode CBR Constant Bit Rate CDV Cell Delay Variation CPE Customer Premises Equipment CRC Cyclic Redundancy Check CTC Common Transmit Clock DSU Data Service Unit FE Far End GSM Group State Machine ...
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... OCD anomaly persists for the period of time specified in ITU-T Recommendation I.432(30)¸. The LCD defect is cleared when the OCD anomaly has not been detected for the period of time specified in ITU-T Recommendation I.432. MT90221 The ICP ‘Stuff‘ Functions ...
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... MT90221 LCD Remote Failure Indication (LCD-RFI) - The LCD-RFI is reported to the FE when a link defect is locally detected. The LCD-RFI defect is not always required on the link interface. Link Delay Synchronization (LDS) - The LDS is an event indicating that the link is synchronized with the other links within the IMA Group with respect to differential delay ...
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... Notes: MT90221 105 ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...