MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 101

• Manufacturer Part Number: MT90221
• Description: Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
• Manufacturer: Zarlink Semiconductor

MT90221
9.1
CPU Interface Timing
The CPU Interface of the MT90221 supports both
the Motorola and Intel timing modes. No Mode
Select pin is required.
With Motorola devices, the Motorola R/W-signal is
connected to the UP_R/W* pin and the UP_OE* pin
is tied to ground. There is no DS signal and the
UP_CS* signal is taken to be qualified with the DS
signal.
When used with Intel devices, the READ-signal is
connected to the UP_OE* pin and the WRITE-signal
is connected to the UP_R/W* pin.
When performing a read operation, data is placed on
the bus immediately after UP_CS* is LOW for the
Motorola timing mode and after the UP_CS* and
UP_OE*signals are LOW for Intel timing.
When performing a write operation in Motorola
timing mode, the data is clocked into an MT90221
pre-load register on the rising edge of the UP_CS*
signal. In Intel timing mode, the data is clocked into
MT90221 pre-load register on the rising edge of the
UP_R/W* signal. Right after that transition, the data
is transferred to the MT90221’s internal register.
Writing data into the this register can take up 2
system clock cycles.
92