MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 82

• Manufacturer Part Number: MT90221
• Description: Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
• Manufacturer: Zarlink Semiconductor

Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Bit #
Bit #
Bit #
7:0
7:4
3:0
7
6
a. Bit 7 is present only for Link 0. In all other Link Status Registers, this bit is set to 0.
b. Bit 6 is present only for Link 0. In all other Link Status Registers, this bit is set to 0.
5
4
3
2
1
0
a
b
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
Each bit set to ’1’ will enable the generation of the interrupt when the corresponding bit in
the IRQ Link Status register is set.
A ’1’ in this bit means that at least one of the IRQ sources from the IMA Group Overflow
Status Register is requesting service. This bit can be cleared only by service the source
of the IRQ.
This bit is valid only for the IRQ Link 0 Status register and is reading always a 0 for the
IRQ Link 1-3 Status registers.
A 1 in this bit means that at least one of the Ready bit used to initiate a transfer of a TX
ICP cell for at least 1 of the IMA Group is returned to 1 (meaning that the transfer of the
TX ICP cell is complete) or a frame pulse was detected for an IMA Group. This bit is
cleared by writing a 0 to it.
This bit is valid only for the IRQ Link 0 Status register and is reading always a 0 for the
IRQ Link 1-3 Status registers.
ICP Cell with changes received. The link has received an ICP cell which contain one or
more changes in it. This status bit can be cleared by writing a ’0’ to it. This bit is set when
an ICP Cell buffer as defined in RX ICP Cell type ram register 1 or 2.
IV. The Link has received an ICP cell which contain a violation as defined in Table 16 of
IMA Spec. This status bit can be cleared by writing a ’0’ to it.
LODS. The Link is Out of Delay Synchronization. This status bit can be cleared by writing
a ’0’ to it.
LIF. Loss of IMA Frame. This status bit can be cleared by writing a ’0’ to it.
LCD Loss of Cell Delineation. This status bit can be cleared by writing a ’0’ to it.
Link Counter Overflow Interrupt. One or more counters associated with the link
overflowed. This status bit can be cleared only by reading or writing to the counter(s)
which is (are) the source for the IRQ.
Reserved.
Each bit set to ’1’ represent an overflow condition from the IMA Group associated with the
bit. There is one bit for each IMA Group. A bit is set when one or more of the 4 counters
or the RX UTOPIA FIFO associated with an IMA Group overflows.
219 - 21C
1 Enable register per link Status reg
00
222 - 225
1 Status register per link
00
235
XD
Table 98 - IRQ IMA Group Overflow Status Register
Table 97 - IRQ Link Enable Registers
Table 96 - IRQ Link Status Registers
Description
Description
Description
MT90221
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