MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 81

• Manufacturer Part Number: MT90221
• Description: Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
• Manufacturer: Zarlink Semiconductor

MT90221
7.11 Interrupt Registers Description
Tables 94 to 102 describe the Interrupt registers.
72
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Bit #
Bit #
7:4
3:0
7:4
3:0
Type
Type
R/W
R/W
R
R
Reserved.
Each bit represents a link. A ’1’ means that the corresponding link has a valid request for
interrupt. The level of the IRQ pin is controlled by the bits in this register and the
corresponding bits in the IRQ Master Enable Register. A write does not have any affect
on the bits in this register. The status bit is not latched and changing the mask bit in the
IRQ Master Register has a direct effect on the level of the IRQ pin.
Reserved. Write 0 for normal operation.
Each bit represents a link. A ’1’ means that the interrupt form the corresponding link is
enabled and that the level of the IRQ pin is low if the corresponding bit in the IRQ Master
Register is set. A ’0’ means that the IRQ level is not affected by the corresponding bit.
232
00
218
00
Table 94 - IRQ Master Status Register
Table 95 - IRQ Master Enable Register
Description
Description