MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 24

• Manufacturer Part Number: MT90221
• Description: Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
• Manufacturer: Zarlink Semiconductor

ATM cells received from the ATM port are placed in a
TX UTOPIA FIFO, waiting to be transmitted. If the
Idle/Unassigned cell removal option is selected,
these cells are dropped. If the TX UTOPIA FIFO is
empty, an Idle cell is sent to the output link. The
content of the Idle cell is pre-initialized with the
header bytes set at 0x00, 0x00, 0x00 and 0x01. The
payload bytes are set to 0x6A.
TX UTOPIA FIFO Length Definition registers are
used to set the TX UTOPIA FIFO size. The total
number of cells in all the TX UTOPIA FIFOs and TX
Link FIFO (includes the links used in IMA Mode and
the links used in UNI Mode) is limited to 58.
Idle Cells are transmitted on the UNI PCM Interface
until the bit corresponding to the link in the UTOPIA
Input Link PHY Enable register is set. Then, the
ATM User cells are transferred from the Input
UTOPIA port to the TX PCM port.
3.0 The ATM Receive Path
The receive path corresponds to the cell flow from
the T1/E1 interfaces to the ATM UTOPIA Interface.
The MT90221 provides cell delineation and optional
cell filtering to discard Unassigned or Idle cells on
each link. The incoming cells are stored in the
external RAM required in IMA mode to perform cell
recovery due to delay variation between the links
introduced by the network.
3.1
This block provides the circuitry necessary to
perform functions such as Cell Delineation (CD), cell
payload de-scrambling, HEC verification and filtering
of Idle (UNI) cells. The CD circuit delineates ATM
cells received from the payload of the T1 or E1 frame
through the PCM Interface.
When
calculations
ATM In
Cell Delineation Function
performing
are
Output Controller and
Cell_In_Control
Cell Distribution
Figure 4 - Functional Block Diagram of the Transmitter in UNI Mode
interpreted
delineation,
to
correct
indicate
(For Link[N] where 1
HEC
cell
boundaries. The CD circuit performs a sequential
byte by byte hunt for a correct HEC sequence. While
performing this hunt, the cell delineation state
machine is in the HUNT state. Figure 5 depicts a
state diagram of the cell delineation operation.
When a correct HEC is found, the CD circuit locks on
the cell boundary and enters the PRESYNC state.
The PRESYNC state keeps checking the HEC to
ensure that the previous indication was not false.
False indications are interpreted to mean the circuit
is not tracking good ATM cells. After entering the
PRESYNC state, the first false indication triggers a
transition back to HUNT state.
If the PRESYNC state HEC is correct, then a
transition to the SYNC state occurs after “ ” cells
(DELTA in ITU I.432) are correctly received. In the
SYNC state, the CD circuit treats the incoming ATM
cell stream as stable and the MT90221 functions
normally.
While in the SYNC state, if an incorrect HEC is
obtained “a” consecutive times (ALPHA in ITU I.432),
cell delineation is considered lost and a transition is
made back to the HUNT state (see Figure 6).
As defined by the ITU I.432 recommendations, the
value
robustness of the delineation method. The value of
ALPHA and DELTA for the Cell Delineation state
machine are defined in the Cell Delineation register.
Consecutive
Incorrect HEC
(cell by cell)
ALPHA
Tx Link [N] FIFO
Transmitter
Figure 5 - Cell Delineation State Diagram
Cell RAM
HUNT
of
N
ALPHA
4)
Correct HEC (byte by byte)
Incorrect HEC
(cell by cell)
SYNC
and
P/S
DELTA
DELTA Consecutive
MT90221
determine
Correct HEC
(cell by cell)
PRESYNC
Serial
Streams
Link [N]
the
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