MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 39

• Manufacturer Part Number: MT90221
• Description: Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
• Manufacturer: Zarlink Semiconductor

MT90221
period and position of the TXSYNC is verified for
each transmit block independently. A status bit (1 per
link) in the TX Sync Status register is set if the
synchronization pulse occurs at an unexpected time
in the frame. The TX block will be re-aligned with this
new synchronization pulse.
4.3.3
Two output pins are provided to simplify the external
circuitry required when using an external PLL. These
two pins, PLLREF0 and PLLREF1, re-route any of
the four RXCK signals and drive the primary and
secondary reference signals of a PLL under software
control. Refer to Section 8, Application Notes, for
examples.
4.3.4
The MT90221 implements circuitry to determine
whether or not a selected clock signal is active. This
feature is used to ensure a clock is operational
before using it as a source for one or more transmit
links. The identity of the clock source to be verified is
written to the Clock Activity register. A read of the
same register indicates clock activity if bit 7 is ’1’. A
value of ’0’ for bit 7 means that no transition was
observed on this clock. This circuitry does not
measure the frequency of a clock signal, it only
detects activity on the four RXCK, four TXCK and
four REFCK signals.
4.3.5
In normal operation, the clock selection circuitry
selects the desired clock signal and ensures a
smooth, glitch free, transition between the current
clock source and the new clock source.
However, if the current clock source is inactive (i.e.,
no clock transitions), the clock select circuitry must
be reset before another clock can be used as
reference. Clock select circuitry is reset by writing a
1 to bit 7 of the PLL Reference Control register.
Clock source activity can be verified using the Clock
Activity register as described in 4.3.4 Verification of
Clock Activity.
5.0 UTOPIA Interface Operation
The MT90221 supports the UTOPIA L2 Mode for cell
level handshake only. Each port can be assigned an
address ranging from 0 to 30. The address value of
31 is reserved and should not be used for any
MT90221 port.
The TX and RX paths of each IMA Group and each
link in UNI has its own PHY address. These PHY
addresses are defined in the UTOPIA Input link
30
Primary and Secondary Reference Signals
Verification of Clock Activity
Clock Selection
Address registers 1 to 4, UTOPIA Input Group
Address register 1 to 4, UTOPIA Output link
Address registers 1 to 4, and the UTOPIA Output
Group Address registers 1 to 4. The UTOPIA Input
LINK PHY Enable and the UTOPIA Output Link
PHY Enable registers are used to enable the PHY
Address of the links in UNI. The UTOPIA Input
Group PHY Enable register and the UTOPIA
Output Group PHY Enable registers are used to
enable the PHY Address of the IMA Groups.
The MT90221 port uses handshaking signals to
process data streams. The start of a cell (SOC) is
marked by the UTOPIA SOC sync signal. This signal
is active during the transfer of the first byte of a cell.
The 52 bytes that follow the arrival of the first byte of
a cell are interpreted as belonging to the same cell
and are stored accordingly (note that SOC sync
signals received during the loading of these 52 bytes
are ignored).
The cell available satus line (Clav) is used to
communicate to the ATM controller if the MT90220
has space for a cell in the PHY address that was
polled in the previous cycle. Whenever there is
space for a cell in teh TX direction or a cell ready in
the RX direction, the TXClav and/or RXClav signal
will be driven High or Low. When the address does
not correspond to any enabled PHY address inside
the MT90220, the TXClav and RXClav signal are in
High impedance mode. The use of an external pull-
down may be required for the proper operation of the
Utopia bus.
It should be noted that the bit 6 and 5 of the Test 1
register have to be set to 1 for the proper operation
of the RX Utopia port in MPHY mode.
5.1
The
independent of the system clock. The UTOPIA TxClk
can be up to 25MHz. The incoming cell is stored
directly in the internal TX Cell RAM where the TX
UTOPIA FIFOs are implemented.
The TX byte clock (TxClk) can be up to 25 MHz and
is checked against the system clock. If the incoming
byte clock frequency is lower than 1/128 of the
system clock, bit 2 of the General Status register
will be set. This bit is cleared by overwriting it with 0.
The total space for the UTOPIA input cells for all IMA
Groups and links in UNI mode is 58. These 58 cells
are shared between 8 TX UTOPIA FIFOs and 4 TX
Link FIFOs. The size (length) of each TX UTOPIA
FIFO is defined by writing to the TX UTOPIA FIFO
Length Definition registers. The maximum value is
ATM Input Port
UTOPIA
interface
input
clock
TxClk
is