MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 57

• Manufacturer Part Number: MT90221
• Description: Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
• Manufacturer: Zarlink Semiconductor

MT90221
48
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Bit #
1:0
7
6
5
4
3
2
Bit #
3-0
7:4
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
R/W
R
Reserved, write 0 for normal operation.
Set to 1 to start sending User Cells in IMA mode.
Set to 0 to send always Filler and ICP cells in IMA mode
(Note: in UNI mode, the control to send User cells is implemented with the UTOPIA Input
Link PHY Enable register).
Coset value. A 0 will generate HEC with Coset value, when 1, Coset is not added.
Cell Scrambling. A 1 enables the scrambling of the cells on the link N.
Reserved, must write a 0 for normal operation.
Set to 1 for UNI mode and clear to 0 for IMA mode. Select the IMA group number
BEFORE enabling the IMA mode.
Defines IMA group number when the link is configured in IMA mode. Select the IMA group
number BEFORE enabling the IMA mode. When configuring the link in UNI mode after it
was in IMA mode, do not change the IMA group number until the link is reported in UNI
mode (refer to TX IMA Mode Status Register).
200 - 203
1 register per TX IMA Group
05
0CC - 0CF
1 register per link
04
Unused. Read all 0’s.
Defines the integration period for an IMA Group:
1111: Reserved. Do not use.
1110: 2
1101: 2
1100: 2
1011: 2
1010: 2
1001: 2
1000: 2
0111: 2
0110: 2
0101: 2
0100: 2
0011: 2
0010: 2
0001: 2
0000: 2
Table 34 - TX IDCR Integration Registers
21
20
19
18
17
16
15
14
13
12
11
10
09
08
07
Table 35 - TX Link Control Registers
clock cycles
clock cycles
clock cycles (preferred value for E1)
clock cycles (preferred value for T1 - 24 channels)
clock cycles
clock cycles (preferred value for T1 - 23 channels)
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
Description
Description