MT90221 Zarlink Semiconductor, MT90221 Datasheet - Page 14

• Manufacturer Part Number: MT90221
• Description: Quad Inverse Multiplexing For Atm (IMA) Device With Flexible Ima And Uni Mode
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
44, 45, 46,
47, 48, 49,
55, 56, 57,
58, 59, 60,
61, 62, 63,
162, 163,
164, 165,
166, 169,
170, 171,
172, 175,
176, 177,
178, 179,
182, 183,
184, 185,
136, 143,
198, 199
145, 151
109,116
99,107,
50, 51
64, 65
Pin #
186
187
41
40
39
67
sr_cs_1, 0
up_r/w
up_oe
up_irq
Name
sr_we
up_wr
up_cs
[18:0]
[10:0]
up_rd
DSTo
up_d
up_a
DSTi
sr_a
[7:0]
[3:0]
[3:0]
or
or
I/O
I/O Processor Data Bus. Data Bus to exchange data between the MT90221 and a
O Static Memory Address Bus. The signal is used to select an entry in the external
O Static Memory Read/Not Write. If low, data is written from the MT90221 to the
O Static Memory Chip Control Signal.
O Processor Interrupt Request. If this signal is low, the MT90221 signals to the
O Serial PCM Data Output 3-0. A 1.544 Mbit/s or 2.048 Mbps serial stream which
I
I
I
I
I
static memory.
memory. If high, data is read from the memory to the MT90221.
local processor.
Processor Address Bus. They are used to select the internal registers and
memory positions of the MT90221.
Processor Read/Not Write. Motorola Mode. This is an input signal. If low, data is
written from the processor to the MT90221. If high, data is read from the MT90221
to the processor.
Processor Not Write (Intel Mode). This is an input signal. If low, data is written
from the processor to the MT90221. De-asserting this signal to high will terminate a
write cycle.
Output enable Motorola Mode. This is an input signal. This signal should be tied
to GND for Motorola timing mode.
Processor Not Read (Intel Mode). This is an input signal. If low, data is read from
the MT90221.
Processor Chip Select. This is an active low input signal. If this signal is high, the
MT90221 ignores all other signals on its processor bus. If this signal is low, the
MT90221 accepts the signals on its processor bus. De-asserting this signal to high
will terminate an access cycle.
processor that an interrupt condition is pending inside the MT90221. Otherwise no
interrupt is pending inside the MT90221. Open drain signal.
contain 24 (T1) or 32 (E1) PCM or data channels received on T1 or E1 line. The
output is set to high impedance for unused channels and if the link is not used.
Serial PCM Data Input 3-0. A 1.544 Mbit/s or 2.048 Mbps serial stream which
contains the 24 (T1) or 32 (E1) PCM or data channels on T1 or E1 line.
Processor Interface Signals (see Note 2)
PCM Interface Signals
Description
MT90221
5