MT58L256L32F Micron Semiconductor Products, Inc., MT58L256L32F Datasheet - Page 7

• Manufacturer Part Number: MT58L256L32F
• Description: 8Mb Syncburst SRAM, 3.3V Vdd, 3.3V or 2.5V I/O, Flow-Through,
• Manufacturer: Micron Semiconductor Products, Inc.

TQFP PIN DESCRIPTIONS
8Mb: 512K x 18, 256K x 32/36 Flow-Through SyncBurst SRAM
MT58L512L18F_C.p65 – Rev. 2/02
92
43
92 (S Version) 92 (S Version)
32-35, 44-50, 32-35, 44-50,
80-82, 99,
(T Version)
(S Version)
x18
100
37
36
93
94
87
88
89
98
97
86
83
85
–
–
92
43
81, 82, 99,
x32/x36
(T Version)
(S Version)
100
37
36
93
94
95
96
87
88
89
98
97
86
83
85
SYMBOL
ADSC#
BWa#
BWb#
BWd#
BWE#
BWc#
ADV#
GW#
CE2#
OE#
SA0
SA1
CLK
CE#
CE2
SA
TYPE
Input Synchronous Address Inputs: These inputs are registered and must
Input Synchronous Byte Write Enables: These active LOW inputs allow
Input Byte Write Enable: This active LOW input permits BYTE WRITE
Input Global Write: This active LOW input allows a full 18-, 32- or 36-bit
Input Clock: CLK registers address, data, chip enable, byte write enables
Input Synchronous Chip Enable: This active LOW input is used to enable
Input Synchronous Chip Enable: This active HIGH input is used to enable
Input Output Enable: This active LOW, asynchronous input enables the
Input Synchronous Address Advance: This active LOW input is used to
Input Synchronous Address Status Controller: This active LOW input
Input Synchronous Chip Enable: This active LOW input is used to enable
meet the setup and hold times around the rising edge of CLK. Two
different pinouts are available for the TQFP package.
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa pins and DQPa; BWb# controls DQb pins and
DQPb. For the x32 and x36 versions, BWa# controls DQa pins and
DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins
and DQPc; BWd# controls DQd pins and DQPd. Parity is only
available on the x18 and x36 versions.
operations and must meet the setup and hold times around the
rising edge of CLK.
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
and burst control inputs on its rising edge. All synchronous inputs
must meet setup and hold times around the clock’s rising edge.
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
the device and is sampled only when a new external address is
loaded. CE2# is only available on the S Version.
the device and is sampled only when a new external address is
loaded.
data I/O output drivers.
advance the internal burst counter, controlling burst access after
the external address is loaded. A HIGH on this pin effectively causes
wait states to be generated (no address advance). To ensure use of
correct address during a WRITE cycle, ADV# must be HIGH at the
rising edge of the first clock after an ADSP# cycle is initiated.
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
FLOW-THROUGH SYNCBURST SRAM
7
8Mb: 512K x 18, 256K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
©2002, Micron Technology, Inc.