MT58L256L32F Micron Semiconductor Products, Inc., MT58L256L32F Datasheet - Page 10

• Manufacturer Part Number: MT58L256L32F
• Description: 8Mb Syncburst SRAM, 3.3V Vdd, 3.3V or 2.5V I/O, Flow-Through,
• Manufacturer: Micron Semiconductor Products, Inc.

FBGA PIN DESCRIPTIONS
8Mb: 512K x 18, 256K x 32/36 Flow-Through SyncBurst SRAM
MT58L512L18F_C.p65 – Rev. 2/02
10R, 11A, 11P, 10P, 10R, 11P,
8P, 8R, 9P, 9R,
10A, 10B, 10P, 9R, 10A, 10B,
2A, 2B, 3P,
3R, 4P, 4R,
11H
x18
11R
4A
7A
3A
6A
6R
6P
5B
7B
6B
3B
8B
–
–
2A, 2B, 3P,
3R, 4P, 4R,
8P, 8R, 9P,
x32/x36
11H
11R
5A
4A
7A
3A
6A
6R
6P
5B
4B
7B
6B
3B
8B
SYMBOL
OE#(G#)
BWa#
BWb#
BWd#
BWE#
BWc#
GW#
CE2#
SA0
SA1
CLK
CE#
CE2
SA
ZZ
Input
Input
Input
Input
Input
TYPE
Input
Input
Input
Input
Input
(continued on next page)
Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
Byte Write Enable: This active LOW input permits BYTE WRITE
Synchronous Chip Enable: This active LOW input is used to enable
Synchronous Chip Enable: This active LOW input is used to enable
Snooze Enable: This active HIGH, asynchronous input causes the
Synchronous Address Inputs: These inputs are registered and must
meet the setup and hold times around the rising edge of CLK.
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb. For
the x32 and x36 versions, BWa# controls DQas and DQPa; BWb#
controls DQbs and DQPb; BWc# controls DQc’s and DQPc; BWd#
controls DQds and DQPd. Parity is only available on the x18 and x36
versions.
operations and must meet the setup and hold times around the
rising edge of CLK.
Global Write: This active LOW input allows a full 18-, 32- or 36-bit
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
Clock: This signal registers the address, data, chip enable, byte write
enables, and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
edge.
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
the device and is sampled only when a new external address is
loaded.
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers.
10
FLOW-THROUGH SYNCBURST SRAM
8Mb: 512K x 18, 256K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
©2002, Micron Technology, Inc.