MT58L256L32F Micron Semiconductor Products, Inc., MT58L256L32F Datasheet - Page 11

• Manufacturer Part Number: MT58L256L32F
• Description: 8Mb Syncburst SRAM, 3.3V Vdd, 3.3V or 2.5V I/O, Flow-Through,
• Manufacturer: Micron Semiconductor Products, Inc.

FBGA PIN DESCRIPTIONS (continued)
10L, 10M, 11D, 10L, 10M, 11J,
8Mb: 512K x 18, 256K x 32/36 Flow-Through SyncBurst SRAM
MT58L512L18F_C.p65 – Rev. 2/02
11E, 11F, 11G 11K, 11L, 11M
(a)
1L, 1M, 2D, 10F, 10G, 11D,
4K, 4L, 4M,
4D, 4E, 4F,
4G, 4H, 4J,
8D, 8E, 8F,
8G, 8H, 8J,
8K, 8L, 8M
(b)
2E, 2F, 2G
10J, 10K,
x18
11C
1J, 1K,
9A
8A
1N
9B
1R
–
–
11E, 11F, 11G
(d)
(b)
(a)
4K, 4L, 4M,
1M, 2J, 2K,
1F, 1G, 2D,
4D, 4E, 4F,
4G, 4H, 4J,
8D, 8E, 8F,
8G, 8H, 8J,
8K, 8L, 8M
2E, 2F, 2G
(c)
x32/x36
1J, 1K, 1L,
2L, 2M
10D, 10E,
10J, 10K,
11N
11C
1D, 1E,
9A
8A
1N
9B
1R
1C
SYMBOL
NF/DQPb
NF/DQPd
NF/DQPa
NF/DQPc
ADSC#
ADSP#
MODE
(LB0#)
ADV#
DQb
DQd
DQa
DQc
V
DD
Output Byte “b” is associated with DQbs. For the x32 and x36 versions,
Supply Power Supply: See DC Electrical Characteristics and Operating
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated DQas;
Input
Input
Input
Input
TYPE
NF/
I/O
(continued on next page)
Synchronous Address Advance: This active LOW input is used to
Synchronous Address Status Processor: This active LOW input
Synchronous Address Status Controller: This active LOW input
Mode: This input selects the burst sequence. A LOW on this
advance the internal burst counter, controlling burst access after
the external address is loaded. A HIGH on ADV# effectively causes
wait states to be generated (no address advance). To ensure use of
correct address during a WRITE cycle, ADV# must be HIGH at the
rising edge of the first clock after an ADSP# cycle is initiated.
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent
upon CE#, CE2, and CE2#. ADSP# is ignored if CE# is HIGH. Power-
down state is entered if CE2 is LOW or CE2# is HIGH.
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
input selects “linear burst.” NC or HIGH on this input selects
“interleaved burst.” Do not alter input state while device is
operating.
Byte “a” is associated with DQas; Byte “b” is associated with DQbs;
Byte “c” is associated with DQcs; Byte “d” is associated with DQds.
Input data must meet setup and hold times around the rising edge
of CLK.
No Function/Parity Data I/Os: On the x32 version, these are No
Function (NF). On the x18 version, Byte “a” parity is DQPa; Byte “b”
parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte
“b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.
Conditions for range.
11
FLOW-THROUGH SYNCBURST SRAM
8Mb: 512K x 18, 256K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
©2002, Micron Technology, Inc.