MT54W1MH18B Micron Semiconductor Products, Inc., MT54W1MH18B Datasheet - Page 9

• Manufacturer Part Number: MT54W1MH18B
• Description: 18Mb Qdrii SRAM, 1.8V Vdd, Hstl, 2-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

Table 5:
18Mb: 1.8V V
MT54W1MH18B_H.fm – Rev. H, Pub. 3/03
SYMBOL
CQ#, CQ
BW_#
NW_#
DLL#
TMS
V
TCK
TDI
W#
ZQ
Q_
C#
D_
K#
R#
SA
C
K
REF
DD
, HSTL, QDRIIb2 SRAM
Ball Descriptions
Output
Output
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Synchronous Byte Writes (or Nibble Writes on x8): When LOW, these inputs cause their
respective bytes to be registered and written if W# had initiated a WRITE cycle. These signals
must meet setup and hold times around the rising edges of K and K# for each of the two
rising edges comprising the WRITE cycle. See Ball Layout figures for signal to data
relationships.
Output Clock: This clock pair provides a user-controlled means of tuning device output data.
The rising edge of C# is used as the output timing reference for first output data. The rising
edge of C is used as the output reference for second output data. Ideally, C# is 180 degrees
out of phase with C. C and C# may be tied HIGH to force the use of K and K# as the output
reference clocks instead of having to provide C and C# clocks. If tied HIGH, these inputs may
not be allowed to toggle during device operation.
Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges
of K and K# during WRITE operations. See Ball Layout figures for ball site location of
individual signals. The x8 device uses D0:D7. Remaining signals are NC. The x18 device uses
D0:D17. Remaining signals are NC. The x36 device uses D0:D35. Remaining signals are NC.
DLL Disable: When LOW, this input causes the DLL to be bypassed for stable, low-frequency
operation.
Input Clock: This input clock pair registers address and control inputs on the rising edge of K,
and registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees
out of phase with K. All synchronous inputs must meet setup and hold times around the clock
rising edges.
Synchronous Read: When LOW, this input causes the address inputs to be registered and a
READ cycle to be initiated. This input must meet setup and hold times around the rising edge
of K and is ignored on the subsequent rising edge of K.
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold
times around the rising edge of K for READ cycles and must meet the setup and hold times
around the rising edge of K# for WRITE cycles. See Ball Layout figures for address expansion
inputs. All transactions operate on a burst of two words (one clock period of bus activity).
These inputs are ignored when both ports are deselected.
IEEE 1149.1 Clock Input: 1.8V I/O levels. This ball must be tied to V
used in the circuit.
IEEE 1149.1 Test Inputs: 1.8V I/O levels. These balls may be left as No Connects if the JTAG
function is not used in the circuit.
HSTL Input Reference Voltage: Nominally V
noise margin. Provides a reference voltage for the HSTL input buffer trip point.
Synchronous Write: When LOW, this input causes the address inputs to be registered and a
WRITE cycle to be initiated. This input must meet setup and hold times around the rising
edge of K.
Output Impedance Matching Input: This input is used to tune the device outputs to the
system data bus impedance. DQ output impedance is set to 0.2 x RQ, where RQ is a resistor
from this ball to ground. Alternately, this ball can be connected directly to V
the minimum impedance mode. This ball cannot be connected directly to GND or left
unconnected.
Synchronous Echo Clock Outputs: The edges of these outputs are tightly matched to the
synchronous data outputs and can be used as data valid indication. These signals run freely
and do not stop when Q tri-states.
Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to K
and K# rising edges if C and C# are tied HIGH. This bus operates in response to R# commands.
See Ball Layout figures for ball site location of individual signals. The x8 device uses Q0:Q7.
Remaining signals are NC. The x18 device uses Q0:Q17. Remaining signals are NC. The x36
device uses Q0:Q35. Remaining signals are NC.
9
2 MEG
1.8V V
DESCRIPTION
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
Q/2, but may be adjusted to improve system
X
8, 1 MEG
DD
, HSTL, QDRIIb2 SRAM
SS
X
if the JTAG function is not
18, 512K
DD
©2003 Micron Technology, Inc.
Q to enable
X
36