MT54W1MH18B Micron Semiconductor Products, Inc., MT54W1MH18B Datasheet - Page 12

• Manufacturer Part Number: MT54W1MH18B
• Description: 18Mb Qdrii SRAM, 1.8V Vdd, Hstl, 2-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

Table 6:
Notes 1–6
Table 7:
Notes 7, 8
NOTE
18Mb: 1.8V V
MT54W1MH18B_H.fm – Rev. H, Pub. 3/03
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW. ­ means rising edge; ¯ means falling edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges, except if C
3. R# and W# must meet setup and hold times around the rising edge (LOW to HIGH) of K and are registered at the ris-
4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most rapid restart by
7. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST WRITE operation
8. This table illustrates operation for x18 devices. The x36 device operation is similar, except for the addition of BW2#
OPERATION
OPERATION
WRITE Cycle:
Load address, input write data on
consecutive K and K# rising edges
READ Cycle:
Load address, output data on consecutive
C and C# rising edges
NOP: No operation
STANDBY: Clock stopped
WRITE D0:17 at K rising edge
WRITE D0:17 at K# rising edge
WRITE D0:8 at K rising edge
WRITE D0:8 at K# rising edge
WRITE D9:17 at K rising edge
WRITE D9:17 at K# rising edge
WRITE nothing at K rising edge
WRITE nothing at K# rising edge
.
and C# are HIGH, then data outputs are delivered at K and K# rising edges.
ing edge of K.
overcoming transmission line charging symmetrically.
provided that the setup and hold requirements are satisfied.
(controls D18:D26) and BW3# (controls D27:D35). The x8 operation is similar, except that NW0# controls D0:D3, and
NW1# controls D4:D7.
:
DD
, HSTL, QDRIIb2 SRAM
Truth Table
BYTE WRITE Operation
Stopped
L®H
L®H
L®H
K
12
R#
2 MEG
H
X
X
L
1.8V V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X
L®H
L®H
L®H
L®H
W#
X
H
X
K
L
8, 1 MEG
DD
, HSTL, QDRIIb2 SRAM
L®H
L®H
L®H
L®H
Q = High-Z
K#
Previous
D OR Q
D
Q
C#(t)­
D = X
K(t)­
State
A
A
at
at
(A0)
X
(A0)
18, 512K
BW0#
0
0
0
0
1
1
1
1
©2003 Micron Technology, Inc.
Q
Q = High-Z
D
K#(t + 1)­
C(t + 1)­
Previous
D OR Q
A
A
D = X
(A0 + 1)
(A0 + 1)
State
at
at
X
BW1#
36
0
0
1
1
0
0
1
1