MT54W1MH18B Micron Semiconductor Products, Inc., MT54W1MH18B Datasheet - Page 20

• Manufacturer Part Number: MT54W1MH18B
• Description: 18Mb Qdrii SRAM, 1.8V Vdd, Hstl, 2-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

Instruction Register
the instruction register. This register is loaded when it
is placed between the TDI and TDO balls, as shown in
Figure 8. Upon power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded
with the IDCODE instruction if the controller is placed
in a reset state, as described in the previous section.
the two LSBs are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test
data path.
Bypass Register
isters, it is sometimes advantageous to skip certain
chips. The bypass register is a single-bit register that
can be placed between the TDI and TDO balls. This
allows data to be shifted through the SRAM with mini-
mal delay. The bypass register is set LOW (Vss) when
the BYPASS instruction is executed.
NOTE
Boundary Scan Register
input and bidirectional balls on the SRAM. The SRAM
has a 107-bit-long register.
tents of the RAM I/O ring when the TAP controller is in
the Capture-DR state and is then placed between the
TDI and TDO balls when the controller is moved to the
18Mb: 1.8V V
MT54W1MH18B_H.fm – Rev. H, Pub. 3/03
TMS
TCK
Three-bit instructions can be serially loaded into
When the TAP controller is in the Capture-IR state,
To save time when serially shifting data through reg-
X = 106.
The boundary scan register is connected to all the
The boundary scan register is loaded with the con-
TDI
:
TAP Controller Block Diagram
DD
, HSTL, QDRIIb2 SRAM
Selection
Circuitry
TAP CONTROLLER
Boundary Scan Register
Figure 8:
31
Identification Register
x
30
Instruction Register
.
29
.
Bypass Register
.
.
.
.
.
.
2
2
2
1
1
1
0
0
0
0
Selection
Circuitry
TDO
20
2 MEG
Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and
SAMPLE Z instructions can be used to capture the
contents of the I/O ring.
which the bits are connected. Each bit corresponds to
one of the balls on the SRAM package. The MSB of the
register is connected to TDI, and the LSB is connected
to TDO.
Identification (ID) Register
bit code during the Capture-DR state when the
IDCODE command is loaded in the instruction regis-
ter. The IDCODE is hardwired into the SRAM and can
be shifted out when the TAP controller is in the Shift-
DR state. The ID register has a vendor code and other
information described in the Identification Register
Definitions table.
TAP Instruction Set
Overview
three-bit instruction register. All combinations are
listed in the Instruction Codes table. Three of these
instructions are listed as RESERVED and should not be
used. The other five instructions are described in detail
below.
compliant to the 1149.1 convention because some of
the mandatory 1149.1 instructions are not fully imple-
mented. The TAP controller cannot be used to load
address, data or control signals into the SRAM and
cannot preload the I/O buffers. The SRAM does not
implement the 1149.1 commands EXTEST or INTEST
or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the I/O ring when these
instructions are executed.
EXTEST
to be executed whenever the instruction register is
loaded with all 0s. EXTEST is not implemented in this
SRAM TAP controller; therefore, this device is not
1149.1-compliant.
tion. When an EXTEST instruction is loaded into the
instruction register, the SRAM responds as if a
SAMPLE/PRELOAD instruction has been loaded.
EXTEST does not place the SRAM outputs (including
CQ and CQ#) in a High-Z state.
The Boundary Scan Order tables show the order in
The ID register is loaded with a vendor-specific, 32-
Eight different instructions are possible with the
The TAP controller used in this SRAM is not fully
EXTEST is a mandatory 1149.1 instruction which is
The TAP controller does recognize an all-0 instruc-
1.8V V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X
8, 1 MEG
DD
, HSTL, QDRIIb2 SRAM
X
18, 512K
©2003 Micron Technology, Inc.
X
36