MT54W1MH18B Micron Semiconductor Products, Inc., MT54W1MH18B Datasheet - Page 2

• Manufacturer Part Number: MT54W1MH18B
• Description: 18Mb Qdrii SRAM, 1.8V Vdd, Hstl, 2-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

for each port (read R#, write W#) which are received at
K rising edge. Port selects permit independent port
operation.
trolled by the K or K# input clock rising edges. Active
LOW byte writes (BWx#) permit byte or nibble write
selection. Write data and byte writes are registered on
the rising edges of both K and K#. The addressing
within each burst of two is fixed and sequential, begin-
ning with the lowest and ending with the highest
address. All synchronous data outputs pass through
output registers controlled by the rising edges of the
output clocks (C and C# if provided, otherwise K and
K#).
ties: test mode select (TMS), test data-in (TDI), test
clock (TCK), and test data-out (TDO). JTAG circuitry is
used to serially shift data to and from the SRAM. JTAG
inputs use JEDEC-standard 1.8V I/O levels to shift data
during this testing mode of operation.
all inputs and outputs are HSTL-compatible. The
device is ideally suited for applications that benefit
from a high-speed, fully-utilized DDR data bus.
sramds) for the latest data sheet.
READ/WRITE Operations
burst of two data, requiring one full clock cycle of bus
utilization. The resulting benefit is that short data
transactions can remain in operation on both buses
provided that the address rate can be maintained by
the system (2x the clock frequency).
18Mb: 1.8V V
MT54W1MH18B_H.fm – Rev. H, Pub. 3/03
Depth expansion is accomplished with port selects
All synchronous inputs pass through registers con-
Four balls are used to implement JTAG test capabili-
The SRAM operates from a 1.8V power supply, and
Please refer to Micron’s Web site
All bus transactions operate on an uninterruptable
DD
, HSTL, QDRIIb2 SRAM
(www.micron.com/
2
2 MEG
by asserting R# LOW at K rising edge. Data is delivered
after the next rising edge of the next K# (t + 1), using C
and C# as the output timing references; or K and K#, if
C and C# are tied HIGH. If C and C# are tied HIGH,
they may not be toggled during device operation. Out-
put tri-stating is automatically controlled such that the
bus is released if no data is being delivered. This per-
mits banked SRAM systems with no complex output
enable (OE) timing generation. Back-to-back READ
cycles are initiated every K rising edge.
edge. The addresses for the WRITE cycle is provided at
the following K# rising edge. Data is expected at the
rising edge of K and K#, beginning at the same K that
initiated the cycle. Write registers are incorporated to
facilitate pipelined, self-timed WRITE cycles and pro-
vide fully coherent data for all combinations of reads
and writes. A read can immediately follow a write, even
if they are to the same address. Although the write data
has not been written to the memory array, the SRAM
will deliver the data from the write register instead of
using the older data from the memory array. The latest
data is always utilized for all bus transactions. WRITE
cycles can be initiated on every K rising edge.
PARTIAL WRITE Operations
the x8 devices in which nibble write is supported. The
active LOW byte write controls, BWx# (NW#), are regis-
tered coincident with their corresponding data. This
feature can eliminate the need for some READ-MOD-
IFY-WRITE cycles, collapsing it to a single BYTE/NIB-
BLE WRITE operation in some instances.
READ cycles are pipelined. The request is initiated
WRITE cycles are initiated by W# LOW at K rising
BYTE WRITE operations are supported except for
1.8V V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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8, 1 MEG
DD
, HSTL, QDRIIb2 SRAM
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18, 512K
©2003 Micron Technology, Inc.
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