MT54W1MH18B Micron Semiconductor Products, Inc., MT54W1MH18B Datasheet - Page 16

• Manufacturer Part Number: MT54W1MH18B
• Description: 18Mb Qdrii SRAM, 1.8V Vdd, Hstl, 2-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

Notes
18Mb: 1.8V V
MT54W1MH18B_H.fm – Rev. H, Pub. 3/03
10. Typical values are measured at V
11. NOP currents are valid when entering NOP after
2. Outputs are impedance-controlled. I
3. All voltages referenced to V
9. I
1. Outputs
4. Overshoot: V
5. AC load current is higher than the shown DC val-
6. HSTL outputs meet JEDEC HSTL Class I and Class
7. The nominal value of V
8. To maintain a valid level, the transitioning edge of
(V
2)/(RQ/5) for values of 175 W £ RQ £ 350 W .
Undershoot: V
Power-up:
and V
During normal operation, V
V
widths less than
rates less than
ues. AC I/O curves are available upon request.
II standards.
range of 1.5V to 1.8V DC, and the variation of
V
the input must:
a. Sustain a constant slew rate from the current AC
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to
ear with frequency. Typical value is measured at
6ns cycle time.
1.5V, and temperature = 25°C.
all pending READ and WRITE cycles are com-
pleted.
DD
DD
DD
DD
DD
V
maintain at least the target DC level, V
V
level through the target AC level, V
, HSTL, QDRIIb2 SRAM
is specified with no output current. I
. R# and W# signals may not have pulse
Q must be limited to ±0.1V DC.
IH
IH
Q/2)/(RQ/5) for values of 175 W £ RQ £ 350 W .
DD
(
(
AC
DC
Q £ 1.4V for t £ 200ms
).
).
are
V
IH
IH
IL
t
KHKH (MIN).
impedance-controlled.
(
(
AC
t
£ V
AC
KHKL (MIN) or operate at cycle
) ³ -0.5V for t £
) £ V
DD
DD
Q + 0.3V and V
DD
Q may be set within the
SS
+ 0.7V for t £
DD
(GND).
Q must not exceed
DD
t
KHKH/2
= 1.8V, V
OL
DD
= (V
t
KHKH/2
DD
IL
IL
|I
(
OH
(
£ 1.7V
AC
DD
DC
is lin-
DD
|
) or
) or
Q =
Q/
=
16
2 MEG
12. Average I/O current and power is provided for
13. This parameter is sampled.
14. Average thermal resistance between the die and
15. Junction temperature is a function of total device
16. This is a synchronous device. All addresses, data,
17. Test conditions as specified with the output load-
18. Control input signals may not be operated with
19. If C and C# are tied HIGH, then K and K# become
20. The device will operate at clock frequencies
21. Clock phase jitter is the variance from clock rising
22. V
23. Echo clock is tightly controlled to data valid/data
1.8V V
informational purposes only and is not tested.
Calculation assumes that all outputs are loaded
with C
of outputs toggle at each transition (n = 18 for the
x36), C
tions: Average I/O Power as dissipated by the
SRAM is: P = 0.5 × n × f × V
Average IDDQ = n × f × V
the case top surface per MIL SPEC 883 Method
1012.1.
power dissipation and device mounting environ-
ment. Measured per SEMI G38-87.
and control lines must meet the specified setup
and hold times for all latching clock edges.
ing as shown in Figure 5 unless otherwise noted.
pulse widths less than
the references for C and C# timing parameters.
slower than
Note TN-54-02 for more information.
edge to the next expected clock rising edge.
for DLL lock retention. DLL lock time begins once
V
hold. By design, there is a ±0.1ns variation from
echo clock to data. The data sheet parameters
reflect tester guardbands and test setup varia-
tions.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
DD
slew rate must be less than 0.1V DC per 50ns
and input clock are stable.
X
L
O
(in farads), f = input clock frequency, half
8, 1 MEG
DD
= 6pF, V
, HSTL, QDRIIb2 SRAM
t
KHKH (MAX). See Micron Technical
DD
Q = 1.5V and uses the equa-
t
KHKL (MIN).
X
DD
18, 512K
DD
Q x (C
Q
2
x (C
L
©2003 Micron Technology, Inc.
+ C
L
+ 2C
O
).
X
O
).
36