MT54W1MH18B Micron Semiconductor Products, Inc., MT54W1MH18B Datasheet - Page 5

• Manufacturer Part Number: MT54W1MH18B
• Description: 18Mb Qdrii SRAM, 1.8V Vdd, Hstl, 2-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

NOTE
18Mb: 1.8V V
MT54W1MH18B_H.fm – Rev. H, Pub. 3/03
1. In this approach, the second clock pair drives the C and C# clocks but is delayed such that return data meets data
2. Consult Micron Technical Notes for more thorough discussions of clocking schemes.
3. Data capture is possible using only one of the two signals. CQ and CQ# clocks are optional use outputs.
4. For high frequency applications (200 MHz and faster) the CQ and CQ# clocks (for data capture) are recommended
MASTER
ASIC)
setup and hold times at the bus master.
over the C and C# clocks (for data alignment). The C and C# clocks are optional use inputs.
(CPU
BUS
or
:
DD
, HSTL, QDRIIb2 SRAM
Delayed K#
DATA OUT
Delayed K
Source K#
Source K
DATA IN
Address
Write#
Read#
BW#
Vt
R
R
R = 50Ω
D
SA
Figure 3: Application Example
Vt = V
R
#
W
#
SRAM #1
REF
W
B
#
/2
C C#
K
5
ZQ
K#
Q
2 MEG
R = 250Ω
1.8V V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X
8, 1 MEG
DD
, HSTL, QDRIIb2 SRAM
D
SA
R
Vt
Vt
R
#
X
W
SRAM #4
#
18, 512K
W
B
#
C C#
©2003 Micron Technology, Inc.
K
ZQ
K#
Q
X
R = 250Ω
36