MCMC68HC05L16 Freescale Semiconductor, Inc, MCMC68HC05L16 Datasheet - Page 88

• Manufacturer Part Number: MCMC68HC05L16
• Description: M68hc05 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Timer System
9.3.4 Timer Counter Register 2
TCNT2 is incremented by the falling edge of the timer clock, which is synchronized and has the same
timing as the falling edge of PH2.
The TCNT2 register is compared with the OC2 buffer register and initialized to $01 if it matches. It is also
initialized to $01 on reset and any CPU write to this register.
The CPU read of this counter should be done while PH2 is high. Data may be latched by the local or main
data bus while PH2 is low.
9.3.5 Timebase Control Register 1
T2R1/T2R0 — Prescale Rate Select Bits for Timer 2
88
The T2R1 and T2R0 bits select prescale rate of CLK2 for timer 2 and timer input 2. These bits are
cleared on reset.
Address:
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
Figure 9-12. Timebase Control Register 1 (TBCR1)
TBCLK
$001F
$0010
BIT 7
BIt 7
BIt 7
Figure 9-11. Timer Counter Register 2 (TCNT2)
0
0
Table 9-2. Timebase Prescale Rate Selection
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
T2R1
0
0
1
1
BIT 6
6
0
6
0
0
LCLK
BIT 5
5
0
5
0
T2R0
0
1
0
1
BIT 4
4
0
4
0
0
BIT 3
3
0
3
0
0
System Clock
Divided by
BIT 2
256
32
1
4
2
0
2
0
0
T2R1
BIT 1
1
0
1
0
Freescale Semiconductor
T2R0
BIT 0
Bit 0
Bit 0
1
0