MCMC68HC05L16 Freescale Semiconductor, Inc, MCMC68HC05L16 Datasheet - Page 74

• Manufacturer Part Number: MCMC68HC05L16
• Description: M68hc05 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Simple Serial Peripheral Interface (SSPI)
Bits 3–1 — Reserved
SPR — SSPI Clock Rate Select
8.6.2 Serial Peripheral Status Register
SPIF — Serial Transfer Complete Flag
DCOL — Data COLlision
Bits 5–0 — Reserved
74
These bits are not used and are fixed to 0.
This serial peripheral clock rate bit selects one of two bit rates of SCK. This bit is cleared on reset.
The serial peripheral data transfer complete flag bit notifies the user that a data transfer between the
MC68HC05L16 and an external device has been completed. With the completion of the data transfer,
the rising edge of the eighth pulse sets SPIF, and if SPIE is set, SSPI is generated. However, during
STOP, the interrupt request is serviced only in slave mode. STOP execution never affects the SPIF
flag or SPIE.
When SPIF is set, the ninth clock from the clock generator or from the SCK pin is inhibited.
Clearing the SPIF bit is done by a software sequence of accessing the SPSR while the SPIF bit is set
followed by accessing SPDR (8-bit shift register). This also clears the DCOL bit. While SPIF is set, all
writes to the SPDR are inhibited until SPSR is read by the CPU.
The SPIF bit is a read-only bit and is cleared on reset.
The data collision bit notifies the user that an attempt was made to write or read the serial peripheral
data register while a data transfer was taking place with an external device. The transfer continues
uninterrupted; therefore, a write will be unsuccessful, and a data read will be incorrect.
A data collision only sets the DCOL bit and does not generate an SSPI interrupt. The DCOL bit
indicates only the occurrence of data collision.
Clearing the DCOL bit is done by a software sequence of accessing the SPSR while SPIF is set
followed by accessing the SPDR. Both the SPIF and DCOL bits will be cleared by this sequence.
The DCOL bit is cleared on reset.
These bits are not used and are fixed to 0.
0 = Internal processor clock divided by 2
1 = Internal processor clock divided by 16
0 = Data transfer not complete
1 = Data transfer complete
0 = No data collision
1 = Data collision occurred
Address:
Reset:
Read:
Write:
$000B
SPIF
Bit 7
Figure 8-5. Serial Peripheral Status Register (SPSR)
0
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
= Unimplemented
DCOL
6
0
5
0
0
4
0
0
3
0
0
2
0
0
1
0
0
Freescale Semiconductor
Bit 0
0
0