MCMC68HC05L16 Freescale Semiconductor, Inc, MCMC68HC05L16 Datasheet - Page 73

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MCMC68HC05L16

Manufacturer Part Number
MCMC68HC05L16
Description
M68hc05 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
8.6 Registers
Three registers in the SSPI provide control, status, and data storage functions. They are:
8.6.1 Serial Peripheral Control Register
SPIE — SSPI Interrupt Enable
SPE — SSPI Enable
DORD — Data Transmission ORDer
MSTR — MaSTeR Mode Select
Freescale Semiconductor
If the serial peripheral interrupt enable (SPIE) bit is set, an interrupt is generated when SPIF in the
SPSR is set and I bit (interrupt mask bit) in the condition code register (CCR) is clear.
During stop mode, an SSPI request is accepted only in slave mode. Interrupt in master mode will be
pending until stop mode is exited. STOP instruction does not change SPIF and SPIE.
When the SSPI enable (SPE) bit is set, the SSPI system is enabled and connected to the port C pins.
Clearing the SPE bit initializes all control logic in the SSPI modules and disconnects the SSPI from
port C pins.
This bit is cleared on reset.
When this bit is set, the data in the 8-bit shift register (SPDR) is shifted in/out from the LSB. When this
bit is cleared, the data in the SPDR is shifted in/out from the MSB.
This bit is cleared on reset.
The MSTR bit determines whether the device is in master mode or slave mode.
In master mode (MSTR = 1), the SCK pin is configured as an output and the serial clock is generated
by the internal clock generator when the CPU writes to the SPDR.
In slave mode (MSTR = 0), the SCK pin is configured as an input and the serial clock is applied
externally. This bit is cleared on reset.
0 = Disable SSPI interrupt
1 = Enable SSPI interrupt
0 = Disable SSPI
1 = Enable SSPI
0 = MSB first
1 = LSB first
0 = Slave mode
1 = Master mode
Serial peripheral control register, SPCR location $000A
Serial peripheral status register, SPSR location $000B
Serial peripheral data register, SPDR location $000C
Address:
Reset:
Read:
Write:
$000A
SPIE
Figure 8-4. Serial Peripheral Control Register (SPCR)
Bit 7
0
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
SPE
6
0
DORD
5
0
MSTR
4
0
3
0
0
2
0
0
1
0
0
Bit 0
SPR
0
Registers
73

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