MCMC68HC05L16 Freescale Semiconductor, Inc, MCMC68HC05L16 Datasheet - Page 63

• Manufacturer Part Number: MCMC68HC05L16
• Description: M68hc05 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

7.5 Timebase
Timebase is a 14-bit up-counter which is clocked by XOSC input or OSC input divided by 128. TBCLK bit
in the TBCR1 register selects the clock source.
This 14-bit divider is initialized to $0078 only upon power-on reset (POR). After counting 8072 clocks, the
STUP bit in the MISC register is set.
The divided clocks from the timebase are used for LCDCLK, STUP, TBI, and COP. (See
7.5.1 LCDCLK
The clocks divided by 64 and 128 are used as LCD clocks at the LCD driver module, and clocks are
selected by the LCLK bit in the TBCR1.
7.5.2 STUP
Timebase divider is initialized to $0078 by the power-on detection. When the count reaches 8072, the
STUP flag in the MISC register is set. Once the STUP flag is set, it is never cleared until power down.
7.5.3 TBI
Timebase interrupts may be generated every 0.5, 0.25, 0.125, or 0.0039 seconds with a 32.768-kHz
crystal at XOSC pins.
The timebase interrupt flag (TBIF) is set every period and interrupt is requested if the enable bit (TBIE) is
set. The clock divided by 128, 4096, 8192, or 16,384 is used to set TBIF, and this clock is selected by the
TBR1 and TBR0 bits in the TBCR2 register. (See
Freescale Semiconductor
OSC/2
XCLK
7
1
0
TBCLK
SEL
COP ENABLE
COP CLEAR
DIVIDER
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
7-BIT
Figure 7-4. Timebase Clock Divider
1/2
1/2
6
7
0
1
LCLK
SEL
Table
DIVIDER
7-3.)
7-BIT
DIVIDE BY 4
1/2
1/2
1/2
1/2
0
5
6
7
TBR1
TBR0
SEL
LCD
CLOCK
Figure
COP
RESET
TBIE
TBIF
Timebase
7-4).
TBI
63