MCMC68HC05L16 Freescale Semiconductor, Inc, MCMC68HC05L16 Datasheet - Page 39

• Manufacturer Part Number: MCMC68HC05L16
• Description: M68hc05 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 4
Resets and Interrupts
4.1 Introduction
In user operating modes, the reset/interrupt vectors are located at the top of the address space
($FFF0–$FFFF). In self-check mode, the reset/interrupt vectors are located at $FFE0–$FFEF in the
internal self-check ROM. Descriptions in this section assume a user operating mode is in use.
shows the address assignments for the vectors.
Upon reset, the I bit in the condition code register is set and interrupts are disabled (masked). When an
interrupt occurs, the I bit is set automatically by hardware after stacking the condition code register (CCR).
All interrupts in the MC68HC05L16 follow a fixed hardware priority circuit to resolve simultaneous
requests.
Each interrupt has a software programmable interrupt mask bit which may be used to selectively inhibit
automatic hardware response. In addition, the I bit in the CCR acts as a class inhibit mask to inhibit all
sources in the I-bit class. RESET and software interrupt (SWI) are not masked by the I bit in the CCR.
SWI is an instruction rather than a prioritized asynchronous interrupt source. In a sense, it is lower in
priority than any source because once any interrupt sequence has begun, SWI cannot override it. In
another sense, it is higher in priority than any hardware sources, except reset, because once the SWI
opcode is fetched, no other sources can be honored until after the first instruction in the SWI service
routine has been executed. SWI causes the I mask bit in the CCR to be set.
Freescale Semiconductor
FFFC–FFFD
FFFE–FFFF
FFFA–FFFB
FFF0–FFF1
FFF2–FFF3
FFF4–FFF5
FFF6–FFF7
FFF8–FFF9
Address
Vector
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
Timebase
SSPI
Timer 2
Timer 1
KWI
IRQ
SWI
Reset
Table 4-1. Interrupt Vector Assignments
Interrupt Source
RESET Pin
Power-On
OC2I
OC1I
IRQ1
IRQ2
COP
TI2I
TOI
ICI
Masked
None
None
None
None
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
I Bit
by
OC2IE
OC1IE
IRQ1E
IRQ2E
COPE
Local
KWIE
Mask
TI2IE
None
None
None
SPIE
TOIE
TBIE
ICIE
Same Level as
(1 = Highest)
an Instruction
Priority
7
6
5
5
4
4
4
3
2
2
1
1
1
Table 4-1
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