MCMC68HC05L16 Freescale Semiconductor, Inc, MCMC68HC05L16 Datasheet
MCMC68HC05L16
Related parts for MCMC68HC05L16
MCMC68HC05L16 Summary of contents
Page 1
MC68HC05L16 MC68HC705L16 Data Sheet M68HC05 Microcontrollers MC68HC05L16 Rev. 4.1 9/2005 freescale.com ...
Page 2
Blank ...
Page 3
... Reformatted to add additional page references and correct World Wide 4.0 2002 Web address September, 4.1 Updated to meet Freescale identity guidelines. 2005 Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2005. All rights reserved. MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor Description Page Number(s) N/A ...
Page 4
Revision History MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1 4 Freescale Semiconductor ...
Page 5
List of Chapters Chapter 1 General Description ...
Page 6
List of Chapters MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1 6 Freescale Semiconductor ...
Page 7
Table of Contents 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 8
Table of Contents 2.4 Option Map for I/O Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 9
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 10
Table of Contents 8.4.3 SPCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 11
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 12
Table of Contents A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 13
Chapter 1 General Description 1.1 Introduction The MC68HC05L16 is an 80-pin microcontroller unit (MCU) with highly sophisticated on-chip peripheral functions. The memory map includes 16 Kbytes of user ROM and 512 bytes of RAM. The MCU has five parallel ports: ...
Page 14
General Description OSC1 OSC OSC2 XOSC1 XOSC XOSC2 COP SYSTEM CPU CONTROL RESET V CPU REGISTERS NDLY** CONDITION CODE REG VLCD3 VLCD2 VLCD1 * Open Drain Only when Output ** The NDLY pin should be connected to ...
Page 15
Mask Options The three mask options on the MC68HC05L16 are: 1. RSTR: RESET pin pullup resistor 2. OSCR: OSC feedback resistor 3. XOSCR: XOSC feedback/damping resistor See 2.4.6 Mask Option Status 1.5 Functional Pin Description The MC68HC05L16 is available ...
Page 16
General Description Pin SCM, Number Self-Check 23 PA0 24 PA1 25 PA2 26 PA3 27 PA4 28 PA5 29 PA6 30 PA7 31 PB0/KWI0 32 PB1/KWI1 PB2/KWI2 33 34 PB3/KWI3 35 PB4/KWI4 36 PB5/KWI5 37 PB6/KWI6 38 PB7/KWI7 39 PC0/SDI ...
Page 17
V and Power is supplied to the MCU through V MCU operates from a single power supply. Very fast signal transitions occur on the MCU pins. The short rise and fall times place very high short-duration ...
Page 18
General Description 1.5.2.2 External Clock An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the OSC2 input not connected, as shown in oscillator is set up. 1.5.3 XOSC1 and XOSC2 The XOSC1 and XOSC2 ...
Page 19
External Clock An external clock from another CMOS-compatible device can be connected to the XOSC1 input, with the XOSC2 input not connected, as shown in the oscillator is set up. 1.5.4 RESET This pin can be used as an ...
Page 20
General Description 1.5.9 Port E (PE0–PE7/FP38–FP35) Port 8-bit output-only port that shares its bits with LCD frontplane drivers. Port E lines are configured as LCD outputs during power-on or reset. PE0–PE3 and PE4–PE7 outputs may be configured ...
Page 21
RESET IRQ1 IRQ2 TST DD 1.6.2 Single-Chip Mode (SCM) In this mode, all address and data bus activity occurs within the MCU. Thus, no external pins are required for these functions. The single-chip mode allows ...
Page 22
General Description MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1 22 Freescale Semiconductor ...
Page 23
Chapter 2 Memory Map 2.1 Introduction The MC68HC05L16 contains a 16,384-byte mask ROM, 496 bytes of self-check ROM, and 512 bytes of RAM. An additional 16 bytes of mask ROM are provided for user vectors at $FFF0–$FFFF. The MCU’s memory ...
Page 24
Memory Map 2.2 Input/Output and Control Registers The input/output (I/O) and control registers reside in locations $0000–$003F. A summary of these registers is shown in Figure 2-3. The bit assignments for each register are shown in from unimplemented bits (denoted ...
Page 25
Option Map Address locations $0000–$000F are dual mapped. When the OPTM bit in the MISC register is cleared, the main address map is accessed. When the OPTM bit in the MISC register is set, the option address map is ...
Page 26
Memory Map Addr. Register Name Serial Peripheral Status Register $000B (SPSR) See page 74. Serial Peripheral Data Register (SP- $000C DR) See page 75. $000D Reserved ↓ $000F Reserved Timebase Control Register 1 $0010 (TBCR1) See page 88. Timebase Control ...
Page 27
Addr. Register Name Timer Counter Register Low $0019 (TCNTL) See page 88. Alternate Timer Counter Register $001A High (ACNTH) See page 79. Alternate Timer Counter Register $001B Low (ACMTL) See page 79. Timer Control Register 2 $001C (TCR2) See page ...
Page 28
Memory Map Addr. Register Name LCD Data Register 5 $0025 (LCDR5) See page 101. LCD Data Register 6 $0026 (LCDR6) See page 101. LCD Data Register 7 $0027 (LCDR7) See page 101. LCD Data Register 8 $0028 (LCDR8) See page ...
Page 29
Addr. Register Name LCD Data Register 17 $0031 (LCDR17) See page 101. LCD Data Register 18 (LCDR18) $0032 See page 101. LCD Data Register 19 $0033 (LCDR19) See page 101. LCD Data Register 20 $0034 (LCDR20) See page 101. $0035 ...
Page 30
Memory Map Addr. Register Name Port A Data Direction Register $0000 (DDRA) See page 52. $0001 Reserved Port C Data Direction Register $0002 (DDRC) See page 55. Port D MUX Register $0003 (PDMUX) See page 56. Port E MUX Register ...
Page 31
Resistor Control Register 1 Address: Option Map — $0008 Bit 7 Read: 0 Write: Reset: 0 Figure 2-5. Resistor Control Register 1 (RCR1) Bits 7–4 — Reserved These bits are not used and always read as logic 0. RBH ...
Page 32
Memory Map 2.4.3 Open-Drain Output Control Register 1 Address: Option Map — $000A Bit 7 Read: DWOMH Write: Reset: 0 Figure 2-7. Open-Drain Output Control Register 1 (WOM1) DWOMH — Port D Open-Drain Mode (H) When this bit is set, ...
Page 33
CWOMx — Port C Open-Drain Mode (Bitx) When CWOMx bit is set, port C bits x are configured as open-drain outputs if DDRCx is set. This bit is cleared on reset. 2.4.5 Key Wakeup Input Enable Register Address: Option Map ...
Page 34
Memory Map 2.5 RAM The 512-byte internal RAM is positioned at $0040–$023F in the memory map. The lower 192 bytes are positioned in the page zero which are accessible by the direct addressing mode. The upper 64 bytes of this ...
Page 35
Chapter 3 Central Processor Unit (CPU) 3.1 Introduction This section describes the central processor unit (CPU). 3.2 CPU Registers The MCU contains five registers as shown in Figure 3- INCREASING MEMORY ADDRESSES UNSTACK NOTE: ...
Page 36
Central Processor Unit (CPU) 3.3 Accumulator The accumulator ( general-purpose, 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. 3.4 Index Register The index register ( 8-bit register used for the ...
Page 37
Stack Pointer The stack pointer (SP) contains the address of the next free location on the stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $00FF. The stack pointer ...
Page 38
Central Processor Unit (CPU) MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1 38 Freescale Semiconductor ...
Page 39
Chapter 4 Resets and Interrupts 4.1 Introduction In user operating modes, the reset/interrupt vectors are located at the top of the address space ($FFF0–$FFFF). In self-check mode, the reset/interrupt vectors are located at $FFE0–$FFEF in the internal self-check ROM. Descriptions ...
Page 40
Resets and Interrupts 4.2 Interrupts There are six hardware interrupt sources in the MC68HC05L16: • IRQ1 and IRQ2 • Key wakeup interrupt (KWI) • Timer 1 (TOI, ICI, and OC1I) • Timer 2 (TI2I and OC2I) • Serial transfer complete ...
Page 41
Figure 4-2 shows an example of IRQ1 interrupt. In this case, the interrupt occurs after execution the instruction following the instruction which sets IRQ1E bit. The similar action occurs against IRQ2 and KWI interrupts CLI BSET IRQ1E, INTCR ...
Page 42
Resets and Interrupts Y Y RESTORE REGISTERS FROM STACK: CCR KWI, timer 1, timer 2, SSPI, and TBI MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1 42 FROM RESET I BIT IN CCR SET ? N IRQ ...
Page 43
IRQ1 C (PC7) R RESET/POR RITE 1 TO RIRQ1 IRQ1E IRQ2E WRITE 1 TO RESET/POR R IRQ2 C (PC6 Figure 4-5. IRQ1 and IRQ2 Block Diagram MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1 Freescale ...
Page 44
Resets and Interrupts KWI0 C (PB0 KWI1 C (PB1) R KWI2 TO KWI6 KWI7 C (PB7) R RESET/POR WRITE 1 TO RKWIF KWIE MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1 ...
Page 45
Interrupt Control Register Address: $0008 Bit 7 Read: IRQ1E Write: Reset: 0 Figure 4-7. Interrupt Control Register (INTCR) IRQ1E — IRQ1 Interrupt Enable The IRQ1E bit enables IRQ1 interrupt when IRQ1F is set. This bit is cleared on reset. ...
Page 46
Resets and Interrupts 4.4 Interrupt Status Register Address: $0009 Bit 7 Read: IRQ1F Write: Reset Unimplemented Figure 4-8. Interrupt Status Register (INTSR) IRQ1F — IRQ1 Interrupt Flag When IRQ1S = 0, the falling edge or low level at ...
Page 47
Chapter 5 Low-Power Modes 5.1 Introduction The MCU has two power-saving modes, stop and wait. Flowcharts of these modes are shown in Figure 5-2. 5.2 Stop Mode The STOP instruction places the MCU in its lowest-power mode. In stop mode, ...
Page 48
Low-Power Modes STATE A CPU: PH2: X1: X2: STATE B CPU: RUN PH2: X1/4 X1: ON X2: ON STATE D CPU: PH2: X1: X2: X1EN = 0 STATE E CPU: PH2: X1: X2: Notes: PH2 is at same frequency as ...
Page 49
STOP OSCILLATOR AND ALL CLOCKS EXCEPT XOSC CLEAR I BIT RESET? N EXTERNAL Y INTERRUPT IRQ? N KWI Y INTERRUPT ? N SSPI Y † INTERRUPT ? N Y TIMEBASE INTERRUPT ‡ FOSC = 1 TURN ON ...
Page 50
Low-Power Modes MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1 50 Freescale Semiconductor ...
Page 51
Chapter 6 Parallel Input/Output (I/O) 6.1 Introduction The MCU has five parallel ports: • Port A has eight I/O pins. • Port B has eight input/only pins. • Port C has eight I/O pins. • Port D has seven output-only ...
Page 52
Parallel Input/Output (I/O) 6.2 Port A Port 8-bit, bidirectional, general-purpose port. The data direction of a port A pin is determined by its corresponding DDRA bit. When a port A pin is programmed as an output by ...
Page 53
DDRAx — Port A Data Direction Register Bit Configure I/O pin PAx to input 1 = Configure I/O pin PAx to output 6.3 Port B Port B pins serve two basic functions: KWI input pins and general-purpose ...
Page 54
Parallel Input/Output (I/O) The PC4 and PC3 pins share functions with the timer input pins (EVI and TCAP). These bits are not affected by the usage of timer input functions and the directions of pins are always controlled by the ...
Page 55
Port C Data Direction Register Address: Option Map — $0002 Bit 7 Read: DDRC7 Write: Reset: 0 Figure 6-6. Port C Data Direction Register (DDRC) Read Anytime when OPTM = 1 Write Anytime when OPTM = 1 Reset Cleared ...
Page 56
Parallel Input/Output (I/O) 6.5.1 Port D Data Register Address: $0003 Bit 7 Read: PD7 Write: Reset: 1 Figure 6-7. Port D Data Register (PORTD) Read Anytime; returns output data latch; bit 0 is always read logic 1 Write Anytime (Writes ...
Page 57
On reset, all port E outputs are disconnected from the pins and the port E data latches are set to logic 1. If EWOMH bit or EWOML bit in the WOM1 register is set, the P-channel driver of output buffers ...
Page 58
Parallel Input/Output (I/O) MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1 58 Freescale Semiconductor ...
Page 59
Chapter 7 Oscillators/Clock Distributions 7.1 Introduction There are two oscillator blocks: OSC and XOSC. Several combinations of the clock distributions are allowed for the modules in the MC68HC05L16. Refer to FOSCE/ PWRON OSC1 OSC OSC2 STOP XOSC1 XOSC XOSC2 7.2 ...
Page 60
Oscillators/Clock Distributions 7.3 System Clock Control The system clock is provided for all internal modules except timebase. Both OSC and XOSC are available as the system clock source. The divide ratio is selected by the SYS1 and SYS0 bits in ...
Page 61
OSC OSC1 R MASK OPTION Figure 7-2. OSC1, OSC2, XOSC1, and XOSC2 Mask Options 7.4.2 XOSC on Line If XOSC is the system clock (SYS:SYS1 = 1:1), OSC can be stopped either by the STOP instruction or by clearing the ...
Page 62
Oscillators/Clock Distributions 7.4.2.2 XOSC with FOSCE = 0 If XOSC is the system clock, clearing FOSCE will stop OSC and preset the 7-bit divider and 6-bit POR counter to $0078. Execution will continue with XOSC and when FOSCE is set ...
Page 63
Timebase Timebase is a 14-bit up-counter which is clocked by XOSC input or OSC input divided by 128. TBCLK bit in the TBCR1 register selects the clock source. This 14-bit divider is initialized to $0078 only upon power-on reset ...
Page 64
Oscillators/Clock Distributions Table 7-3. Timebase Interrupt Frequency TBCR2 Divide Ratio TBR TBR 1 0 TBCLK ÷ 128 0 0 TBCLK ÷ 4096 0 1 TBCLK ÷ 8192 1 0 TBCLK ÷ 16,384 1 1 7.5.4 COP The computer operating properly ...
Page 65
Timebase Control Register 1 Address: $0010 Bit 7 Read: TBCLK Write: Reset: 0 Figure 7-5. Timebase Control Register 1 (TBCR1) Read Anytime Write Anytime (Only one write is allowed on bit 7 after reset.) TBCLK — Timebase Clock The ...
Page 66
Oscillators/Clock Distributions 7.5.6 Timebase Control Register 2 Address: $0011 Bit 7 Read: TBIF Write: Reset Unimplemented Figure 7-6. Timebase Control Register 2 (TBCR2) Read Anytime (Bits 3 and 0 are write-only bits and always read as logic 0.) ...
Page 67
COPE — COP Enable When the COPE bit is logic 1, the COP reset function is enabled. This bit is cleared on reset (including COP timeout reset) and write to this bit is allowed only once after reset. COPC — ...
Page 68
Oscillators/Clock Distributions Table 7-6. System Bus Clock Frequency Selection SYS1 SYS0 Divide Ratio OSC ÷ OSC ÷ OSC ÷ XOSC ÷ FOSCE — Fast (Main) Oscillator Enable The ...
Page 69
Chapter 8 Simple Serial Peripheral Interface (SSPI) 8.1 Introduction The simple serial peripheral interface (SSPI) of the MC68HC05L16 is a master/slave synchronous serial communication module. SSPI uses a 3-wire protocol: data input, data output, and serial clock. In this format, ...
Page 70
Simple Serial Peripheral Interface (SSPI) After 8-bit data is shifted in/out, SCK stops and SPIF is set. If SPIE is enabled, an interrupt request is generated. The slave device in stop mode wakes up by this interrupt. Further transfers (writes ...
Page 71
Control This block is an interface to the HC05 internal bus and generates a start signal when a write to the SPDR is detected in master mode. It also generates an interrupt request to the CPU. 8.4.2 SPDR This ...
Page 72
Simple Serial Peripheral Interface (SSPI) SCK SDO DORD = 0 SDI DORD = 0 SDO DORD = 1 SDI DORD = 1 DATA SAMPLE Figure 8-3. SSPI Clock-Data Timing Diagram 8.5.2 Serial Clock (SCK) SCK is used for synchronization of ...
Page 73
Registers Three registers in the SSPI provide control, status, and data storage functions. They are: • Serial peripheral control register, SPCR location $000A • Serial peripheral status register, SPSR location $000B • Serial peripheral data register, SPDR location $000C ...
Page 74
Simple Serial Peripheral Interface (SSPI) Bits 3–1 — Reserved These bits are not used and are fixed to 0. SPR — SSPI Clock Rate Select This serial peripheral clock rate bit selects one of two bit rates of SCK. This ...
Page 75
Serial Peripheral Data Register Address: $000C Bit 7 Read: MSB Write: Reset: Figure 8-6. Serial Peripheral Data Register (SPDR) Read A read during transmission causes DCOL to be set. Write A write during transmission causes DCOL to be set. ...
Page 76
Simple Serial Peripheral Interface (SSPI) MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1 76 Freescale Semiconductor ...
Page 77
Chapter 9 Timer System 9.1 Introduction The MC68HC05L16 has two timer modules: timer 1 with a 16-bit counter and timer 2 with an 8-bit counter. Timer 1 has one input pin (TCAP) and no output pin. Timer 2 has one ...
Page 78
Timer System HIGH LOW BYTE BYTE $16 OUTPUT $17 COMPARE REGISTER OUTPUT COMPARE CIRCUIT TIMER ICF OCF TOF STATUS REGULAR INTERRUPT CIRCUIT Because the timer has a 16-bit architecture, each specific functional segment (capability) is represented by two registers. These ...
Page 79
Counter The key element in the programmable timer is a 16-bit, free-running counter or counter register preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the timer a resolution of 2.0 microseconds if ...
Page 80
Timer System 9.2.3 Input Capture Register Two 8-bit registers, which make up the 16-bit input capture register, are read-only and are used to latch the value of the free-running counter after the corresponding input capture edge detector senses a defined ...
Page 81
IEDG — Input Edge The value of the input edge determines which level transition on the TCAP pin will trigger free-running counter transfer to the input capture register. Reset does not affect the IEDG bit Negative edge 1 ...
Page 82
Timer System 9.2.6 Timer During Wait Mode The CPU clock halts during wait mode, but timer 1 remains active. If interrupts are enabled, a timer interrupt will cause the processor to exit wait mode. 9.2.7 Timer During Stop Mode In ...
Page 83
OC2 = FF, 0 COUNT UP COMPARE PH2 TIMCLK COUNTER2 OC2 (BUFFER) CMP2 EVO OC2 = 1 COUNT UP COMPARE PH2 TIMCLK PRESET COUNTER2 OC2 (BUFFER) CMP2 EVO Figure 9-6. Timer 2 Timing Diagram ...
Page 84
Timer System OC2 = FF, 0 PH2 TIMCLK COUNTER2 OC2 (BUFFER) CMP2 EVO Legend: COUNT UP COMPARE PRESET that overrides COUNT UP OC2 = 1 PH2 TIMCLK COUNTER2 OC2 (BUFFER) CMP2 EVO Legend: COUNT ...
Page 85
The CLK2 from the prescaler or the EXTCLK from the EVI block is selected as timer clock by the T2CLK bit in the TCR2 register. The CLK2 and the EXCLK are synchronized to the falling edge of system clock in ...
Page 86
Timer System IM2 — Timer Input 2 Mode Select The IM2 bit selects whether EVI input is gated or not gated by CLK2. This bit is cleared on reset EVI not gated by CLK2 (event mode ...
Page 87
Timer Status Register 2 Address: $001D BIt 7 Read: TI2F Write: Reset: 0 Figure 9-9. Timer Status Register 2 (TSR2) TI2F — Timer Input 2 (EVI) Interrupt Flag In event mode, the event edge sets TI2F. In gated time ...
Page 88
Timer System 9.3.4 Timer Counter Register 2 Address: $001F BIt 7 Read: BIT 7 Write: Reset: 0 Figure 9-11. Timer Counter Register 2 (TCNT2) TCNT2 is incremented by the falling edge of the timer clock, which is synchronized and has ...
Page 89
Timer Input 2 (EVI) The event input (EVI) is used as an external clock input for timer 2. PC4 EVI PC4 Since the external clock may be asynchronous to the internal clock, this input has a synchronizer which samples ...
Page 90
Timer System IM2 = 0 Event Mode EVI PH2 EXCLK IL2 = 0 COUNTER EXCLK IL2 = 1 COUNTER IM2 = 1 Gate Mode EVI SYNCHRONIZED CLK2 EXCLK IL2 = 0 COUNTER EXCLK IL2 = 1 COUNTER MC68HC05L16 • MC68HC705L16 ...
Page 91
Event Output (EVO) The EVO pin is the clock output pin of timer 2. The compare output from the timer 2 (CMP2) is divided in this block for 50% duty output signal. This 1/2 divider is initialized to the ...
Page 92
Timer System OL2 = 0 CNTR2 WRITE CMP2 OE2 CMP2/2 PC5 = 0/EVO OL2 = 1 CMP2 OE2 CMP2/2 PC5 = 1/EVO MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1 92 EVO EVO Figure 9-16. EVO Timing Diagram Freescale Semiconductor ...
Page 93
Prescaler The 8-bit prescaler in the timer system divides system clock (PH2) and provides divided clock to each timer and event input. CLK1 for timer fixed frequency clock (PH2/PH4). CLK2 for timer 2 is selected by ...
Page 94
Timer System MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1 94 Freescale Semiconductor ...
Page 95
Chapter 10 LCD Driver 10.1 Introduction The liquid crystal display (LCD) driver may be configured with four backplanes (BP) and 39 frontplanes (FP) maximum. The V voltage is the highest level of the output waveform and the lower three levels ...
Page 96
LCD Driver DUTY = 1/2 BIAS = 1/2 (VLCD1 = VLCD2 = V 1 FRAME BP0 BP1 FPX (XX01) FPY (XX00) BP0–FPX (ON) BP1–FPX (OFF) BP0–FPY (OFF) Figure 10-2. LCD 1/2 Duty and 1/2 Bias Timing Diagram MC68HC05L16 • MC68HC705L16 ...
Page 97
DUTY = 1/3 BIAS = 1/3 (VLCD1 = V BP0 BP1 BP2 FPx (X010) BP0–FPx (OFF) BP1–FPx (ON) Figure 10-3. LCD 1/3 Duty and 1/3 Bias Timing Diagram MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor –VLCD/3, VLCD2 = ...
Page 98
LCD Driver DUTY = 1/4 BIAS = 1/3 (VLCD1 = V BP0 BP1 BP2 BP3 FPX (1001) BP0–FPX (ON) BP1–FPX (OFF) Figure 10-4. LCD 1/4 Duty and 1/3 Bias Timing Diagram MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1 98 –VLCD/3, ...
Page 99
Backplane Driver and Port Selection The number of backplane (port D) pins depends on the LCD duty automatically selected by DUTY1 and DUTY0 bits in the LCD control register (LCDCR). On reset, these bits are cleared and ...
Page 100
LCD Driver 10.5 LCD Control Register Address: $0020 Bit 7 Read: LCDE Write: Reset: 0 Figure 10-5. LCD Control Register (LCDCR) LCDE — LCD Output Enable The LCDE bit enables all BP and FP outputs. (This bit does not affect ...
Page 101
LCD Data Register Address: $0021–$0034 Bit 7 Read: BP3 Write: Reset: LCDRx — LCD Data Registers Data in the LCDRx (LCDR1–LCDR20) controls the waveform of the two frontplane drivers. Bits 0–3 and bits 4–7 of this register decide the ...
Page 102
LCD Driver MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1 102 Freescale Semiconductor ...
Page 103
Chapter 11 Instruction Set 11.1 Introduction The microcontroller unit (MCU) instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS (complementary metal-oxide semiconductor) Family plus one more: the unsigned multiply (MUL) ...
Page 104
Instruction Set 11.2.4 Extended Extended instructions use three bytes and can access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the ...
Page 105
Instruction Types The MCU instructions fall into these five categories: • Register/memory instructions • Read-modify-write instructions • Jump/branch instructions • Bit manipulation instructions • Control instructions 11.3.1 Register/Memory Instructions These instructions operate on central processor unit (CPU) registers and ...
Page 106
Instruction Set 11.3.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. Do not use read-modify-write operations on write-only registers. Table ...
Page 107
Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal ...
Page 108
Instruction Set 11.3.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the ...
Page 109
Instruction Set Summary Table 11-6. Instruction Set Summary (Sheet Source Operation Form ADC #opr ADC opr ADC opr Add with Carry ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr Add without Carry ...
Page 110
Instruction Set Table 11-6. Instruction Set Summary (Sheet Source Operation Form BIT #opr BIT opr BIT opr Bit Test Accumulator with Memory Byte BIT opr,X BIT opr,X BIT ,X BLO rel Branch if Lower (Same as BCS) ...
Page 111
Table 11-6. Instruction Set Summary (Sheet Source Operation Form CLR opr CLRA CLRX Clear Byte CLR opr,X CLR ,X CMP #opr CMP opr CMP opr Compare Accumulator with Memory Byte CMP opr,X CMP opr,X CMP ,X COM ...
Page 112
Instruction Set Table 11-6. Instruction Set Summary (Sheet Source Operation Form LDA #opr LDA opr LDA opr Load Accumulator with Memory Byte LDA opr,X LDA opr,X LDA ,X LDX #opr LDX opr LDX opr Load Index Register ...
Page 113
Table 11-6. Instruction Set Summary (Sheet Source Operation Form RTI Return from Interrupt RTS Return from Subroutine SBC #opr SBC opr SBC opr Subtract Memory Byte and Carry Bit from SBC opr,X Accumulator SBC opr,X SBC ,X ...
Page 114
Instruction Set Table 11-6. Instruction Set Summary (Sheet Source Operation Form TXA Transfer Index Register to Accumulator WAIT Stop CPU Clock and Enable Interrupts A Accumulator C Carry/borrow flag CCR Condition code register dd Direct address of ...
Page 115
Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA 3 DIR 2 DIR 2 REL 2 DIR BRCLR0 ...
Page 116
Instruction Set MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1 116 Freescale Semiconductor ...
Page 117
Chapter 12 Electrical Specifications 12.1 Introduction This section contains parametric and timing information. 12.2 Maximum Ratings Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. The MCU contains circuitry to ...
Page 118
Electrical Specifications 12.3 Operating Temperature Range Characteristic Operating temperature range MC68HC05L16 (standard) MC68HC05L16C (extended) 12.4 Thermal Characteristics Characteristic Thermal resistance 80-pin plastic quad flat pack 12.5 Recommended Operating Conditions (1) Rating Supply voltage Fast clock oscillation frequency External capacitance (f ...
Page 119
DC Electrical Characteristics Characteristic Output voltage = 10.0 µA I Load = –10.0 µA I Load Output high voltage ( –0.4 mA) PA0–PA7, PC0–PC5, PD1–PD7, Load PE0–PE7 Output low voltage (V = ...
Page 120
Electrical Specifications 12.7 3.3-Volt DC Electrical Characteristics Characteristic Output voltage = 10.0 µA I Load = –10.0 µA I Load Output high voltage ( –0.4 mA) PA0–PA7, PC0–PC5, PD1–PD7, PE0–PE7 Load Output low voltage ...
Page 121
DC Electrical Characteristics Characteristic Output voltage = 10.0 µA I Load = –10.0 µA I Load Output high voltage ( –0.4 mA) PA0–PA7, PC0–PC5, PD1–PD7, PE0–PE7 Load Output low voltage (V = ...
Page 122
Electrical Specifications 12.9 Control Timing Characteristic Frequency of oscillation (OSC) Crystal External clock (2) Internal operating frequency , crystal or external clock (f /2) OSC 5.5 V ...
Page 123
OSC1 t RL RESET t ILIH 2 IRQ IRQ 3 INTERNAL CLOCK INTERNAL ADDRESS BUS Notes: 1. Represents the internal gating of the OSC1 pin 2. IRQ pin edge-sensitive mask option 3. IRQ pin level and edge-sensitive mask option ...
Page 124
Electrical Specifications MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1 124 Freescale Semiconductor ...
Page 125
Chapter 13 Mechanical Specifications 13.1 Introduction This section describes the dimensions of the quad flat pack (QFP). MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor 125 ...
Page 126
Mechanical Specifications 13.2 Quad Flat Pack (QFP) — Case 841B- - -D- 0.20 (0.008) 0.05 (0.002) 0.20 (0.008 -C- SEATING H PLANE G DATUM -H- PLANE W X DETAIL C MC68HC05L16 • MC68HC705L16 ...
Page 127
Chapter 14 Ordering Information 14.1 Introduction This section contains instructions for ordering custom-masked ROM MCUs. 14.2 MCU Ordering Forms To initiate an order for a ROM-based MCU, first obtain the current ordering form for the MCU from a Freescale representative. ...
Page 128
Ordering Information On diskettes, the application program must be in Freescale’s S-record format (S1 and S9 records), a character-based object file format generated by M6805 cross assemblers and linkers. Begin the application program at the first user ROM location. Program ...
Page 129
MC Order Numbers Table 14-1 shows the MC order numbers for the available package types. Package Type 80-pin plastic quad flat pack (QFP) MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1 Freescale Semiconductor Table 14-1. MC Order Numbers Operating Temperature ...
Page 130
Ordering Information MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1 130 Freescale Semiconductor ...
Page 131
Appendix A MC68HC705L16 A.1 Introduction The MC68HC705L16 is similar to the MC68HC05L16 with the exception of the EPROM feature. The program ROM on the MC68HC05L16 has been replaced by 16-K electrically programmable read-only memory to allow modification of the program ...
Page 132
MC68HC705L16 OSC1 OSC OSC2 XOSC1 XOSC XOSC2 COP SYSTEM CPU RESET CONTROL M68HC05 CPU CPU REGISTERS PROGRAM COUNTER CONDITION CODE REG VLCD3 VLCD2 VLCD1 * Open drain only when output pin should be ...
Page 133
A.5 Functional Pin Description The MC68HC705L16 is available in the 80-pin quad flat pack (QFP). The pin assignment is shown in Figure A- FP28/PE6 FP29/PE5 FP30/PE4 FP31/PE3 FP32/PE2 FP33/PE1 FP34/PE0 FP35/PD7 FP36/PD6 FP37/PD5 FP38/PD4 VLCD3 VLCD2 ...
Page 134
MC68HC705L16 Pin SCM, Number Bootstrap 23 PA0 24 PA1 25 PA2 26 PA3 27 PA4 28 PA5 29 PA6 30 PA7 31 PB0/KWI0 32 PB1/KWI1 33 PB2/KWI2 34 PB3/KWI3 35 PB4/KWI4 36 PB5/KWI5 37 PB6/KWI6 38 PB7/KWI7 39 PC0/SDI 40 ...
Page 135
A.7 Modes of Operation The MC68HC705L16 has the following operating modes: single-chip mode (SCM) and bootstrap mode. Single-chip mode, also called user mode, allows maximum use of pins for on-chip peripheral functions. The bootstrap mode is provided for EPROM programming, ...
Page 136
MC68HC705L16 A.7.3 Bootstrap Mode In this mode, the reset vector is fetched from a 496-byte internal bootstrap ROM at $FE00–$FFEF. The bootstrap ROM contains a small program which loads a program into the internal RAM and then passes control to ...
Page 137
A.9 Boot ROM Boot ROM is 496 bytes of mask ROM positioned at $FE00–$FFEF. This ROM contains bootstrap loader programs and reset/interrupt vectors in the bootstrap mode. The bootstrap loader programs include: • EPROM programming and verification • Dumping EPROM ...
Page 138
MC68HC705L16 A.10.2 Program Control Register A program control register is provided for EPROM programming. Address: $000D Bit 7 Read: R Write: Reset Figure A-5. Program Control Register (PCR) Bits 7–3 — Reserved These bits are reserved and read ...
Page 139
A.11 LCD 1/2 Duty and 1/2 Bias Timing Diagram DUTY = 1/2 BIAS = 1/2 (VLCD1 = VLCD2 = V BP0 BP1 FPx (XX10) FPy (XX00) BP0–FPx (OFF) BP1–FPx (ON) BP0–FPy (OFF) BP1–FPy (OFF) Figure A-6. CD 1/2 Duty and ...
Page 140
MC68HC705L16 A.12 Electrical Specifications This section contains parametric and timing information for the MC68HC705L16. A.12.1 Maximum Ratings Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. The MCU contains circuitry ...
Page 141
A.12.2 Operating Temperature Range Characteristic Operating temperature range MC68HC705L16 (standard) MC68HC705L16C (extended) A.12.3 Thermal Characteristics Characteristic Thermal resistance 80-pin plastic quad flat pack A.13 Recommended Operating Conditions (1) Rating Supply voltage Fast clock oscillation frequency External capacitance (f = 3.52 ...
Page 142
MC68HC705L16 A.13.2 5.0-Volt DC Electrical Characteristics Characteristic Output voltage = 10.0 µA I Load = –10.0 µA I Load Output high voltage ( –0.4 mA) PA0–PA7, PC0–PC5, PD1–PD7, PE0–PE7 Load Output low voltage (V ...
Page 143
A.13.3 3.3-Volt DC Electrical Characteristics Characteristic Output voltage = 10.0 µA I Load = –10.0 µA I Load Output high voltage ( –0.4 mA) PA0–PA7, PC0–PC5, PD1–PD7, PE0–PE7 Load Output low voltage (V = ...
Page 144
MC68HC705L16 A.13.4 3.3-Volt and 5.0-Volt Control Timing Characteristic Frequency of oscillation (OSC) Crystal External clock (2) Internal operating frequency , crystal or external clock (f /2) OSC ...
Page 145
...
Page 146
... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005. All rights reserved. ...