MCMC68HC05L16 Freescale Semiconductor, Inc, MCMC68HC05L16 Datasheet - Page 81

• Manufacturer Part Number: MCMC68HC05L16
• Description: M68hc05 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

IEDG — Input Edge
Bits 2–4 — Not Used
OLVL — Not Used
9.2.5 Timer Status Register
The TSR is a read-only register containing three status flag bits.
ICF — Input Capture Flag
OC1F — Output Compare 1 Flag
TOF — Timer Overflow Flag
Bits 0–4 — Not Used
Accessing the timer status register satisfies the first condition required to clear status bits. The remaining
step is to access the register corresponding to the status bit.
A problem can occur when using the timer overflow function and reading the free-running counter at
random times to measure an elapsed time. Without incorporating the proper precautions into software,
the timer overflow flag could unintentionally be cleared if:
The counter alternate register at address $1A and $1B contains the same value as the free-running
counter (at address $18 and $19); therefore, this alternate register can be read at any time without
affecting the timer overflow flag in the timer status register.
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1. The timer status register is read or written when TOF is set.
2. The LSB of the free-running counter is read but not for the purpose of servicing the flag.
The value of the input edge determines which level transition on the TCAP pin will trigger free-running
counter transfer to the input capture register.
Reset does not affect the IEDG bit.
Always read logic 0
Always read logic 0
Always read logic 0
0 = Negative edge
1 = Positive edge
0 = Flag cleared when TSR and input capture low register ($15) are accessed
1 = Flag set when selected polarity edge is sensed by input capture edge detector
0 = Flag cleared when TSR and output compare low register ($17) are accessed
1 = Flag set when output compare register contents match the free-running counter contents
0 = Flag cleared when TSR and counter low register ($19) are accessed
1 = Flag set when free-running counter transition from $FFFF to $0000 occurs
Address:
Reset:
Read:
Write:
$0013
Bit 7
ICF
U
MC68HC05L16 • MC68HC705L16 Data Sheet, Rev. 4.1
Figure 9-4. Timer Status Register (TSR)
= Unimplemented
OC1F
U
6
TOF
U
5
U = Unaffected
4
0
0
3
0
0
2
0
0
1
0
0
Bit 0
0
0
Timer 1
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