SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 927

• Manufacturer Part Number: SAM9G15
• Manufacturer: Atmel Corporation

Specifications of SAM9G15

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 6
• Lin: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

41.7.10.1
Figure 41-12. Buffer Structure when TSMODE = 0
41.7.10.2
11053B–ATARM–22-Sep-11
trig.event1
trig.event2
trig.eventN
Assuming ADC_CHSR = 0x000_01600
ADC_EMR(TAG) = 1
DMA Buffer
Structure
Classical ADC Channels Only
TouchScreen Channels Only
5
6
8
5
6
8
5
6
8
on a half-word (16-bit), consists of last converted data right aligned and when TAG is set in
ADC_EMR register, the 4 most significant bits are carrying the channel number thus allowing an
easier post-processing in the DMA buffer or better checking the DMA buffer integrity.
As soon as touchscreen conversions are required, the pen detection function may help the post-
processing of the buffer. To get more details refer to
When no touchscreen conversion is required (i.e. TSMODE = 0 in ADC_TSMR register), the
structure of data within the buffer is defined by the ADC_MR, ADC_CHSR, ADC_SEQR1,
ADC_SEQR2 registers.
If the user sequence is not used (i.e. USEQ is cleared in ADC_MR register) then only the value
of ADC_CHSR register defines the data structure. For each trigger event, enabled channels will
be consecutively stored in ADC_LCDR register and automatically transferred to the buffer.
When the user sequence is configured (i.e. USEQ is set in ADC_MR register) not only does
ADC_CHSR register modify the data structure of the buffer, but ADC_SEQR1, ADC_SEQR2
registers may modify the data structure of the buffer as well.
When only touchscreen conversions are required (i.e. TSMODE differs from 0 in ADC_TSMR
register and ADC_CHSR equals 0), the structure of data within the buffer is defined by the
ADC_TSMR register.
When TSMODE = 1 or 3, each trigger event adds 2 half-words in the buffer (assuming TSAV =
0), first half-word being XPOS of ADC_XPOSR register then YPOS of ADC_YPOSR register. If
TSAV/TSFREQ differs from 0, the data structure remains unchanged. Not all trigger events add
data to the buffer.
ADC_CDR5
ADC_CDR6
ADC_CDR8
ADC_CDR5
ADC_CDR6
ADC_CDR8
ADC_CDR5
ADC_CDR6
ADC_CDR8
Base Address (BA)
BA + 0x02
BA + 0x04
BA + 0x06
BA + 0x08
BA + 0x0A
BA + [(N-1) * 6]
BA + [(N-1) * 6]+ 0x02
BA + [(N-1) * 6]+ 0x04
DMA Transfer
trig.eventN
trig.event1
trig.event2
Assuming ADC_CHSR = 0x000_01600
ADC_EMR(TAG) = 0
DMA Buffer
Structure
Section 41.7.10.4 ”Pen Detection
0
0
0
0
0
0
0
0
0
ADC_CDR5
ADC_CDR6
ADC_CDR8
ADC_CDR5
ADC_CDR6
ADC_CDR8
ADC_CDR5
ADC_CDR6
ADC_CDR8
SAM9G35
Status”.
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