SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 546
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SAM9G15
Manufacturer Part Number
SAM9G15
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G15.pdf
(1211 pages)
5.SAM9G15.pdf
(45 pages)
Specifications of SAM9G15
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
6
Lin
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G15 PDF datasheet #4
- SAM9G15 PDF datasheet #5
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- Download datasheet (30Mb)
33.6.7
546
546
SAM9G35
SAM9G35
Transfer With DMA
Notes:
USB packets of any length may be transferred when required by the UDPHS Device. These
transfers always feature sequential addressing.
Packet data AHB bursts may be locked on a DMA buffer basis for drastic overall AHB bus band-
width performance boost with paged memories. These clock-cycle consuming memory row (or
bank) changes will then likely not occur, or occur only once instead of dozens times, during a
single big USB packet DMA transfer in case another AHB master addresses the memory. This
means up to 128-word single-cycle unbroken AHB bursts for Bulk endpoints and 256-word sin-
gle-cycle unbroken bursts for isochronous endpoints. This maximum burst length is then
contro lled by the lowest programm ed USB endpoint size (EPT_SIZE field in the
U D P H S _ E P T C F G x r e g i s t e r ) a n d D M A S i z e ( B U F F _ L E N G T H f i e l d i n t h e
UDPHS_DMACONTROLx register).
The USB 2.0 device average throughput may be up to nearly 60 MBytes. Its internal slave aver-
age access latency decreases as burst length increases due to the 0 wait-state side effect of
unchanged endpoints. If at least 0 wait-state word burst capability is also provided by the exter-
nal DMA AHB bus slaves, each of both DMA AHB busses need less than 50% bandwidth
allocation for full USB 2.0 bandwidth usage at 30 MHz, and less than 25% at 60 MHz.
The UDPHS DMA Channel Transfer Descriptor is described in
Descriptor” on page
Note:
endpoint 4 memory window. The endpoint 5 does not move and a memory conflict
appears as the memory windows of the endpoints 4 and 5 overlap. The data of these
endpoints is potentially lost.
1. There is no way the data of the endpoint 0 can be lost (except if it is de-allocated) as the mem-
2. Deactivating then reactivating the same endpoint with the same configuration only modifies
3. When the user writes a value different from zero to the
In case of debug, be careful to address the DMA to an SRAM address even if a remap is done.
ory allocation and de-allocation may affect only higher endpoints.
temporarily the controller DPRAM pointer and size for this endpoint. Nothing changes in the
DPRAM, higher endpoints seem not to have been moved and their data is preserved as far as
nothing has been written or received into them while changing the allocation state of the first
endpoint.
field, the Endpoint Mapped bit (UDPHS_EPTCFGx.EPT_MAPD) is set only if the configured
size and number of banks are correct as compared to the endpoint maximal allowed values
and to the maximal FIFO size (i.e. the DPRAM size). The UDPHS_EPTCFGx.EPT_MAPD
value does not consider memory allocation conflicts.
599.
UDPHS_EPTCFGx.BK_NUMBER
“UDPHS DMA Channel Transfer
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
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