SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 451

• Manufacturer Part Number: SAM9G15
• Manufacturer: Atmel Corporation

Specifications of SAM9G15

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 6
• Lin: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

30.6
30.6.1
Table 30-1.
Table 30-2.
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
27
27
26
26
Bk[1:0]
Software Interface/SDRAM Organization, Address Mapping
25
25
SDRAM Address Mapping for 16-bit Memory Data Bus Width and Four Banks
Bk[1:0]
Bk[1:0]
24
24
Linear Mapping for SDRAM Configuration, 2K Rows, 512/1024/2048/4096 Columns
Linear Mapping for SDRAM Configuration: 4K Rows, 512/1024/2048/4096 Columns
Bk[1:0]
Bk[1:0]
23
23
Bk[1:0]
Bk[1:0]
22
22
Bk[1:0]
The SDRAM address space is organized into banks, rows and columns. The DDRSDRC maps
different memory types depending on the values set in the DDRSDRC Configuration Register.
See
trate the relation between CPU addresses and columns, rows and banks addresses for 16-bit
memory data bus widths and 32-bit memory data bus widths.
The DDRSDRC supports address mapping in linear mode and interleaved mode.
Linear mode is a method for address mapping where banks alternate at each last SDRAM page
of current bank.
Interleaved mode is a method for address mapping where banks alternate at each SDRAM end
page of current bank.
The DDRSDRC makes the SDRAM devices access protocol transparent to the user.
to
with the device structure. Various configurations are illustrated.
21
21
Table 30-15
Section 30.7.3 “DDRSDRC Configuration Register” on page
20
20
Row[11:0]
19
19
Row[10:0]
Row[11:0]
18
18
Row[10:0]
illustrate the SDRAM device memory mapping seen by the user in correlation
Row[11:0]
17
17
Row[10:0]
Row[11:0]
16
16
Row[10:0]
15
15
CPU Address Line
CPU Address Line
14
14
13
13
12
12
11
11
10
10
9
9
8
8
Column[11:0]
Column[11:0]
7
7
Column[10:0]
Column[10:0]
458. The following figures illus-
Column[9:0]
Column[9:0]
6
6
Column[8:0]
Column[8:0]
5
5
4
4
SAM9G35
SAM9G35
3
3
2
2
Table 30-1
1
1
M0
M0
M0
M0
M0
M0
M0
M0
451
451
0
0