SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 428
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SAM9G15
Manufacturer Part Number
SAM9G15
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G15.pdf
(1211 pages)
5.SAM9G15.pdf
(45 pages)
Specifications of SAM9G15
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
6
Lin
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G15 PDF datasheet #4
- SAM9G15 PDF datasheet #5
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30.4
30.4.1
428
428
Initialization Sequence
SAM9G35
SAM9G35
SDR-SDRAM Initialization
The addresses given are for example purposes only. The real address depends on implementa-
tion in the product.
The initialization sequence is generated by software. The SDR-SDRAM devices are initialized
by the following sequence:
A minimum pause of 200 μs is provided to precede any signal toggle.
Note:
1. Program the memory device type into the Memory Device Register (see
2. Program the features of the SDR-SDRAM device into the Timing Register (asynchro-
3. For low-power SDRAM, temperature-compensated self refresh (TCSR), drive strength
4. A NOP command is issued to the SDR-SDRAM. Program NOP command into Mode
5. An all banks precharge command is issued to the SDR-SDRAM. Program all banks
6. Eight auto-refresh (CBR) cycles are provided. Program the auto refresh command
7. A Mode Register set (MRS) cycle is issued to program the parameters of the SDR-
8. For low-power SDR-SDRAM initialization, an Extended Mode Register set (EMRS)
9. The application must go into Normal Mode, setting Mode to 0 in the Mode Register (see
on page
nous timing (trc, tras, etc.)), and into the Configuration Register (number of columns,
rows, banks, cas latency) (see
and
(DS) and partial array self refresh (PASR) must be set in the Low-power Register (see
Section 30.7.7 on page
Register, the application must set Mode to 1 in the Mode Register (See
on page
this command. Now the clock which drives SDR-SDRAM device is enabled.
precharge command into Mode Register, the application must set Mode to 2 in the
Mode Register (See
SDRAM address to acknowledge this command.
(CBR) into Mode Register, the application must set Mode to 4 in the Mode Register
(see
tion eight times to acknowledge these commands.
SDRAM devices, in particular CAS latency and burst length. The application must set
Mode to 3 in the Mode Register (see
access to the SDR-SDRAM to acknowledge this command. The write address must be
chosen so that BA[1:0] are set to 0. For example, with a 16-bit 128 MB SDR-SDRAM
(12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done
at the address 0x20000000.
cycle is issued to program the SDR-SDRAM parameters (TCSR, PASR, DS). The appli-
cation must set Mode to 5 in the Mode Register (see
perform a write access to the SDR-SDRAM to acknowledge this command. The write
address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0. For example,
with a 16-bit 128 MB SDRAM, (12 rows, 9 columns, 4 banks) bank address the SDRAM
write access should be done at the address 0x20800000.
Section 30.7.1 on page
to acknowledge this command.
This address is for example purposes only. The real address is dependent on implementation in
the product.
Section 30.7.5 on page
Section 30.7.1 on page
467).
456). Perform a write access to any SDR-SDRAM address to acknowledge
Section 30.7.1 on page
465).
456) and perform a write access at any location in the SDRAM
463).
456).Performs a write access to any SDR-SDRAM loca-
Section 30.7.3 on page
Section 30.7.1 on page
456). Perform a write access to any SDR-
Section 30.7.1 on page
458,
Section 30.7.4 on page 461
456) and perform a write
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Section 30.7.1
Section 30.7.8
456) and
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