SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 1011
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SAM9G15
Manufacturer Part Number
SAM9G15
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G15.pdf
(1211 pages)
5.SAM9G15.pdf
(45 pages)
Specifications of SAM9G15
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
6
Lin
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
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- SAM9261 PDF datasheet #3
- SAM9G15 PDF datasheet #4
- SAM9G15 PDF datasheet #5
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Table 44-1.
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Bit
19:17
13:12
11:0
26
25
24
23
22
21
20
16
15
14
Specific address register 1 match
Specific address register 2 match
Specific address register 3 match
Specific address register 4 match
Type ID match
VLAN tag detected (i.e., type id of 0x8100)
Priority tag detected (i.e., type id of 0x8100 and null VLAN identifier)
VLAN priority (only valid if bit 21 is set)
Concatenation format indicator (CFI) bit (only valid if bit 21 is set)
End of frame - when set the buffer contains the end of a frame. If end of frame is not set, then the only other valid status
are bits 12, 13 and 14.
Start of frame - when set the buffer contains the start of a frame. If both bits 15 and 14 are set, then the buffer contains a
whole frame.
Receive buffer offset - indicates the number of bytes by which the data in the first buffer is offset from the word address.
Updated with the current values of the network configuration register. If jumbo frame mode is enabled through bit 3 of the
network configuration register, then bits 13:12 of the receive buffer descriptor entry are used to indicate bits 13:12 of the
frame length.
Length of frame including FCS (if selected). Bits 13:12 are also used if jumbo frame mode is selected.
Receive Buffer Descriptor Entry (Continued)
To receive frames, the buffer descriptors must be initialized by writing an appropriate address to
bits 31 to 2 in the first word of each list entry. Bit zero must be written with zero. Bit one is the
wrap bit and indicates the last entry in the list.
The start location of the receive buffer descriptor list must be written to the receive buffer queue
pointer register before setting the receive enable bit in the network control register to enable
receive. As soon as the receive block starts writing received frame data to the receive FIFO, the
receive buffer manager reads the first receive buffer location pointed to by the receive buffer
queue pointer register.
If the filter block then indicates that the frame should be copied to memory, the receive data
DMA operation starts writing data into the receive buffer. If an error occurs, the buffer is recov-
ered. If the current buffer pointer has its wrap bit set or is the 1024
buffer location is read from the beginning of the receive descriptor list. Otherwise, the next
receive buffer location is read from the next word in memory.
There is an 11-bit counter to count out the 2048 word locations of a maximum length, receive
buffer descriptor list. This is added with the value originally written to the receive buffer queue
pointer register to produce a pointer into the list. A read of the receive buffer queue pointer reg-
ister returns the pointer value, which is the queue entry currently being accessed. The counter is
reset after receive status is written to a descriptor that has its wrap bit set or rolls over to zero
after 1024 descriptors have been accessed. The value written to the receive buffer pointer regis-
ter may be any word-aligned address, provided that there are at least 2048 word locations
available between the pointer and the top of the memory.
Section 3.6 of the AMBA 2.0 specification states that bursts should not cross 1K boundaries. As
receive buffer manager writes are bursts of two words, to ensure that this does not occur, it is
Function
th
descriptor, the next receive
SAM9G35
SAM9G35
1011
1011
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