SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 309
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SAM9G15
Manufacturer Part Number
SAM9G15
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G15.pdf
(1211 pages)
5.SAM9G15.pdf
(45 pages)
Specifications of SAM9G15
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
6
Lin
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G15 PDF datasheet #4
- SAM9G15 PDF datasheet #5
- Current page: 309 of 1274
- Download datasheet (30Mb)
25.5.4.4
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
SDCS
Hardware Configuration
Software Configuration
A[1..14]
D[0..31]
R2
R2
2x16-bit SDRAM on EBI
0R
0R
VDDIOM
R1
R1
470K
470K
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
SDA10
A13
BA0
BA1
A14
CKE
CLK
DQM0
DQM1
CAS
RAS
WE
The following configuration has to be performed:
The Data Bus Width is to be programmed to 32 bits. The data lines D[16..31] are multiplexed
with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO
controller.
The SDRAM initialization sequence is described in the section “SDRAM Device Initialization” in
“SDRAM Controller (SDRAMC)”.
In this case VDDNF must to be equal to VDDIOM. The NAND Flash device must be 3.3V and
wired on D0-D15 data bus. NFD0_ON_D16 is to be set to 0.
• Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip
• Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency.
SDRAM
23
24
25
26
29
30
31
32
33
34
22
35
20
21
36
40
37
38
15
39
17
18
16
19
Select Assignment Register located in the bus matrix memory space.
MN1
MN1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA0
BA1
A12
N.C1
CKE
CLK
DQML
DQMH
CAS
RAS
WE
CS
MT48LC16M16A2P-75IT
MT48LC16M16A2P-75IT
256 Mbits
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
VDD
VDD
VDD
VSS
VSS
VSS
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
1
14
27
3
9
43
49
28
41
54
6
12
46
52
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
C1
C1
100NF
100NF
VDDIOM
C2
C2
100NF
100NF
C3
C3
100NF
100NF
C4
C4
100NF
100NF
C5
C5
100NF
100NF
C6
C6
100NF
100NF
R4
R4
C7
C7
100NF
100NF
0R
0R
VDDIOM
R3
R3
470K
470K
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
SDA10
A13
BA0
BA1
A14
CKE
CLK
DQM2
DQM3
CAS
RAS
WE
23
24
25
26
29
30
31
32
33
34
22
35
20
21
36
40
37
38
15
39
17
18
16
19
MN2
MN2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA0
BA1
A12
N.C1
CKE
CLK
DQML
DQMH
CAS
RAS
WE
CS
256 Mbits
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
VDD
VDD
VDD
VSS
VSS
VSS
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
1
14
27
3
9
43
49
28
41
54
6
12
46
52
SAM9G35
SAM9G35
C8
C8
100NF
100NF
VDDIOM
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
C9
C9
100NF
100NF
C10
C10
100NF
100NF
C11
C11
100NF
100NF
C12
C12
100NF
100NF
C13
C13
100NF
100NF
309
309
C14
C14
100NF
100NF
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