SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 341

• Manufacturer Part Number: SAM9G15
• Manufacturer: Atmel Corporation

Specifications of SAM9G15

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 105
• Ext Interrupts: 105
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 3
• Uart: 6
• Lin: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

27.4.2
27.4.2.1
Figure 27-5. Read Operation with Spare Decoding
27.4.2.2
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Remainder computation enable signal
Read NAND operation with SPAREEN set to Zero and AUTO set to One
512 or 1024 bytes
MLC/SLC Read Page Operation using PMECC
MLC/SLC Read Operation with Spare Decoding
MLC/SLC Read Operation
Sector 0
Table 27-3.
When the spare area is protected, the spare area contains valid data. As the redundancy may
be included in the middle of the information stream, the user programs the start address and the
end address of the ECC area. The controller will automatically skip the ECC area. This mode is
entered by writing one in the DATA field of the PMECC_CTRL register. When the page has
been fully retrieved from NAND, the ECC area is read using the user mode by writing one to the
USER field of the PMECC_CTRL register.
If the spare area is not protected with the error correcting code, the redundancy area is retrieved
directly. This mode is entered by writing one in the DATA field of the PMECC_CTRL register.
BCH_ERR field
0
1
2
3
4
Sector 1
Relevant Remainders Registers
pagesize = n * sectorsize
Sector size set to 512 bytes
PMECC_REM0
PMECC_REM0, PMECC_REM1
PMECC_REM0, PMECC_REM1,
PMECC_REM2, PMECC_REM3,
PMECC_REM0, PMECC_REM1,
PMECC_REM2, PMECC_REM3,
PMECC_REM4, PMECC_REM5,
PMECC_REM6, PMECC_REM7
PMECC_REM0, PMECC_REM1,
PMECC_REM2, PMECC_REM3,
PMECC_REM4, PMECC_REM5,
PMECC_REM6, PMECC_REM7,
PMECC_REM8, PMECC_REM9,
PMECC_REM10, PMECC_REM11
Sector 2
Sector size set to 1024 bytes
PMECC_REM0
PMECC_REM0, PMECC_REM1
PMECC_REM0, PMECC_REM1,
PMECC_REM2, PMECC_REM3
PMECC_REM0, PMECC_REM1,
PMECC_REM2, PMECC_REM3,
PMECC_REM4, PMECC_REM5,
PMECC_REM6, PMECC_REM7
PMECC_REM0, PMECC_REM1,
PMECC_REM2, PMECC_REM3,
PMECC_REM4, PMECC_REM5,
PMECC_REM6, PMECC_REM7,
PMECC_REM8, PMECC_REM9,
PMECC_REM10, PMECC_REM11
Sector 3
start_addr
ecc_area
sparesize
SAM9G35
SAM9G35
Spare
end_addr
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