SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 303
SAM9G15
Manufacturer Part Number
SAM9G15
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G15.pdf
(1211 pages)
5.SAM9G15.pdf
(45 pages)
Specifications of SAM9G15
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
6
Lin
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G15 PDF datasheet #4
- SAM9G15 PDF datasheet #5
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- Download datasheet (30Mb)
25.5.3.5
25.5.3.6
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Static Memory Controller
DDR2SDRAM Controller
In the following example the NAND Flash and the external RAM (DDR2 or LP-DDR or 16bit LP-
SDR) are NOT in the same power supply range (NFD0_ON_D16 = 1).
This can be used if the SMC connects to the NAND Flash only. Using this function with another
device on the SMC will lead to an unpredictable behavior of that device. In that case, the default
value must be selected.
At reset NFD0_ON_D16 = 0 and NAND Flash bus is connected to D0-D15.
For information on the Static Memory Controller, refer to the Static Memory Controller section.
The product embeds a multi-port DDR2SDR Controller. This allows to use three additional ports
on DDR2SDRC to lessen the EBI load from a part of DDR2 or LP-DDR accesses. This
increases the bandwidth when DDR2 and NAND Flash devices are used. This feature is NOT
compatible with SDR or LP-SDR Memory.
It is controlled by DDR_MP_EN bit in EBI Chip Select Assignment Register.
Figure 25-2. DDR2SDRC Multi-port Enabled (DDR_MP_EN = 1)
Bus Matrix
EBI
D[31:16]
A[22:21]
D[15:0]
DDR2SDRC
Port 3
Port 2
Port 1
Port 0
EBI
16-bit LP-SDR (1.8V)
NAND Flash (3.3V)
ALE
CLE
D[15:0]
D[15:0]
LP-DDR or
DDR2 or
DDR2 or LP-DDR
Device
NAND Flash
Device
SAM9G35
SAM9G35
303
303
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