SAM9G15 Atmel Corporation, SAM9G15 Datasheet - Page 499
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SAM9G15
Manufacturer Part Number
SAM9G15
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G15.pdf
(1211 pages)
5.SAM9G15.pdf
(45 pages)
Specifications of SAM9G15
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
6
Lin
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G15 PDF datasheet #4
- SAM9G15 PDF datasheet #5
- Current page: 499 of 1274
- Download datasheet (30Mb)
Figure 31-14. DMAC Transfer Replay Mode is Enabled for the Source and Contiguous Destination Address
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Multi-buffer DMAC Transfer with Linked List for Source and Contiguous Destination Address (Row 2)
Buffer Transfer Complete
interrupt generated here
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Set up the linked list in memory. Write the control information in the
LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx register location of the buffer descriptor
for each LLI in memory for channel x. For example, in the register, you can program the
following:
a. Set up the transfer type (memory or non-memory peripheral for source and desti-
b. Set up the transfer characteristics, such as:
– i. Transfer width for the source in the SRC_WIDTH field.
– ii. Transfer width for the destination in the DST_WIDTH field.
– iii. Source AHB master interface layer in the SIF field where source resides.
– iv. Destination AHB master interface layer in the DIF field where destination resides.
Channel Disabled by
nation) and flow control device by programming the FC of the DMAC_CTRLBx
register.
Buffer Complete interrupt
hardware
generated here
yes
Contiguous mode for DADDRx
HDMA State Machine Table?
Replay mode for SADDRx,
Stall until STALLED field is
cleared by software writing
DMA_EBCIMR[x]=1?
Channel Enabled by
Is HDMA in Row1of
CTRLAx, CTRLBx
KEEPON Field
Buffer Transfer
software
no
yes
no
SAM9G35
SAM9G35
499
499
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